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Commit 69060d96 authored by Kelvin Gardiner's avatar Kelvin Gardiner Committed by Joonas Lahtinen
Browse files

drm/i915/bdw: Do not write the replay bit of the ring mode register 



The replay bit of the ring mode register is not a valid bit for Gen8+.
Do not write to this bit.

Signed-off-by: default avatarKelvin Gardiner <kelvin.gardiner@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
[Joonas: Fixed commit message line to be under 72 chars]
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487963724-4824-1-git-send-email-kelvin.gardiner@intel.com
parent ca7a45ba

drivers/gpu/drm/i915/intel_lrc.c

+0 −1
Original line number Diff line number Diff line
@@ -1178,7 +1178,6 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) 


	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);

	I915_WRITE(RING_MODE_GEN7(engine),

		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |

		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));

	I915_WRITE(RING_HWS_PGA(engine->mmio_base),

		   engine->status_page.ggtt_offset);