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Commit 688685dc authored by Jennifer L. Zenner's avatar Jennifer L. Zenner
Browse files

msm: ipa3: Add support for IPA/GSI register dump/collection 



Add functionality to the IPA/GSI driver in support of a register
dump/collection feature.  Register's values are collected upon kernel
exception.

Change-Id: I6ccc5a801fd2cf9cd8e92ad4e2c9244a88fae393
CRs-Fixed: 2401867
Signed-off-by: default avatarJennifer L. Zenner <jzenner@codeaurora.org>
parent f5f31790

drivers/platform/msm/Kconfig

+38 −0
Original line number Diff line number Diff line
@@ -182,4 +182,42 @@ config QCOM_GENI_SE 
	  module is used to configure and read the configuration from the

	  Serial Engines.



config IPA3_REGDUMP

	bool "Dump or collect IPA/GSI register values on Linux crash"

	depends on IPA3

	help

	  This option is to be used when the saving of IPA register state is

	  desired upon a fatal system exception. When an exception occurs,

	  an IPA register collection algorithm will be run in the context of

	  the exception handler.  A predefined set of registers will be read

	  and their values will be placed into a static hierarchical data

	  structure that can be perused post crash.



choice

	prompt "Platform whose registers are to be dumped/collected"

	depends on IPA3_REGDUMP

	help

	  The choices within represent the possible platforms this build is

	  intended for. The choices are mutually exclusive.  By selecting

	  one, you effect the inclusion path used, such that the relevant

	  register definitions will be found.  Each platform has unique

	  register definitions.



config IPA3_REGDUMP_IPA_4_5

	bool "The 4.5 IPA"

	depends on IPA3_REGDUMP

	depends on ARCH_KONA

	help

	  Set this to enable the 4.5 IPA's registers to be dumped/collected.



endchoice



config IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS

	int "The number of extra endp registers for remaining pipes"

	depends on IPA3_REGDUMP

	default 0

	help

	  If the platform has extra endpoint registers for remaining

	  pipes, please express how many here.



endmenu

drivers/platform/msm/gsi/gsi.c

+1 −0
Original line number Diff line number Diff line
@@ -2496,6 +2496,7 @@ int gsi_write_channel_scratch3_reg(unsigned long chan_hdl, 
	mutex_unlock(&ctx->mlock);

	return GSI_STATUS_SUCCESS;

}

EXPORT_SYMBOL(gsi_write_channel_scratch3_reg);



static void __gsi_read_channel_scratch(unsigned long chan_hdl,

		union __packed gsi_channel_scratch * val)

drivers/platform/msm/ipa/ipa_v3/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -13,3 +13,7 @@ ipat-$(CONFIG_IPA_EMULATION) += ipa_dt_replacement.o 
obj-$(CONFIG_RMNET_IPA3) += rmnet_ipa.o ipa_qmi_service_v01.o ipa_qmi_service.o rmnet_ipa_fd_ioctl.o



obj-$(CONFIG_IPA3_MHI_PROXY) += ipa_mhi_proxy.o



ipat-$(CONFIG_IPA3_REGDUMP) += dump/ipa_reg_dump.o



ccflags-$(CONFIG_IPA3_REGDUMP_IPA_4_5) += -Idrivers/platform/msm/ipa/ipa_v3/dump/ipa4.5

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio.h

0 → 100644
+2392 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio_def.h

0 → 100644
+520 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */

#if !defined(_GSI_HWIO_DEF_H_)

#define _GSI_HWIO_DEF_H_

struct gsi_hwio_def_gsi_cfg_s {

	u32	gsi_enable : 1;

	u32	mcs_enable : 1;

	u32	double_mcs_clk_freq : 1;

	u32	uc_is_mcs : 1;

	u32	gsi_pwr_clps : 1;

	u32	bp_mtrix_disable : 1;

	u32	reserved0 : 2;

	u32	sleep_clk_div : 4;

	u32	reserved1 : 20;

};

union gsi_hwio_def_gsi_cfg_u {

	struct gsi_hwio_def_gsi_cfg_s	def;

	u32				value;

};

struct gsi_hwio_def_gsi_ree_cfg_s {

	u32	move_to_esc_clr_mode_trsh : 1;

	u32	channel_empty_int_enable : 1;

	u32	reserved0 : 6;

	u32	max_burst_size : 8;

	u32	reserved1 : 16;

};

union gsi_hwio_def_gsi_ree_cfg_u {

	struct gsi_hwio_def_gsi_ree_cfg_s	def;

	u32					value;

};

struct gsi_hwio_def_gsi_manager_ee_qos_n_s {

	u32	ee_prio : 2;

	u32	reserved0 : 6;

	u32	max_ch_alloc : 5;

	u32	reserved1 : 3;

	u32	max_ev_alloc : 5;

	u32	reserved2 : 11;

};

union gsi_hwio_def_gsi_manager_ee_qos_n_u {

	struct gsi_hwio_def_gsi_manager_ee_qos_n_s	def;

	u32						value;

};

struct gsi_hwio_def_gsi_shram_n_s {

	u32 shram : 32;

};

union gsi_hwio_def_gsi_shram_n_u {

	struct gsi_hwio_def_gsi_shram_n_s	def;

	u32					value;

};

struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s {

	u32	phy_ch : 5;

	u32	valid : 1;

	u32	reserved0 : 26;

};

union gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_u {

	struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s	def;

	u32							value;

};

struct gsi_hwio_def_gsi_test_bus_sel_s {

	u32	gsi_testbus_sel : 8;

	u32	reserved0 : 8;

	u32	gsi_hw_events_sel : 4;

	u32	reserved1 : 12;

};

union gsi_hwio_def_gsi_test_bus_sel_u {

	struct gsi_hwio_def_gsi_test_bus_sel_s	def;

	u32					value;

};

struct gsi_hwio_def_gsi_test_bus_reg_s {

	u32 gsi_testbus_reg : 32;

};

union gsi_hwio_def_gsi_test_bus_reg_u {

	struct gsi_hwio_def_gsi_test_bus_reg_s	def;

	u32					value;

};

struct gsi_hwio_def_gsi_debug_countern_s {

	u32	counter_value : 16;

	u32	reserved0 : 16;

};

union gsi_hwio_def_gsi_debug_countern_u {

	struct gsi_hwio_def_gsi_debug_countern_s	def;

	u32						value;

};

struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s {

	u32 rf_reg : 32;

};

union gsi_hwio_def_gsi_debug_sw_rf_n_read_u {

	struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s	def;

	u32						value;

};

struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s {

	u32	phy_ev_ch : 5;

	u32	valid : 1;

	u32	reserved0 : 26;

};

union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u {

	struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s {

	u32	chtype_protocol : 3;

	u32	chtype_dir : 1;

	u32	ee : 4;

	u32	chid : 5;

	u32	chtype_protocol_msb : 1;

	u32	erindex : 5;

	u32	reserved0 : 1;

	u32	chstate : 4;

	u32	element_size : 8;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s {

	u32	r_length : 16;

	u32	reserved0 : 16;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s {

	u32 r_base_addr_lsbs : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s {

	u32 r_base_addr_msbs : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s {

	u32 read_ptr_lsb : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s {

	u32 read_ptr_msb : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s {

	u32 write_ptr_lsb : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s {

	u32 write_ptr_msb : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s {

	u32	read_ptr : 16;

	u32	reserved0 : 16;

};

union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s {

	u32	re_intr_db : 16;

	u32	reserved0 : 16;

};

union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s {

	u32	wrr_weight : 4;

	u32	reserved0 : 4;

	u32	max_prefetch : 1;

	u32	use_db_eng : 1;

	u32	prefetch_mode : 4;

	u32	reserved1 : 2;

	u32	empty_lvl_thrshold : 8;

	u32	reserved2 : 8;

};

union gsi_hwio_def_ee_n_gsi_ch_k_qos_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def;

	u32					value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u {

	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s {

	u32	chtype : 4;

	u32	ee : 4;

	u32	evchid : 8;

	u32	intype : 1;

	u32	reserved0 : 3;

	u32	chstate : 4;

	u32	element_size : 8;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s {

	u32	r_length : 16;

	u32	reserved0 : 16;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s {

	u32 r_base_addr_lsbs : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s {

	u32 r_base_addr_msbs : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s {

	u32 read_ptr_lsb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s {

	u32 read_ptr_msb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s {

	u32 write_ptr_lsb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s {

	u32 write_ptr_msb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s {

	u32	int_modt : 16;

	u32	int_modc : 8;

	u32	int_mod_cnt : 8;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s {

	u32 intvec : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s {

	u32 msi_addr_lsb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s {

	u32 msi_addr_msb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s {

	u32 rp_update_addr_lsb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s {

	u32 rp_update_addr_msb : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u {

	struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_gsi_status_s {

	u32	enabled : 1;

	u32	reserved0 : 31;

};

union gsi_hwio_def_ee_n_gsi_status_u {

	struct gsi_hwio_def_ee_n_gsi_status_s	def;

	u32					value;

};

struct gsi_hwio_def_ee_n_cntxt_type_irq_s {

	u32	ch_ctrl : 1;

	u32	ev_ctrl : 1;

	u32	glob_ee : 1;

	u32	ieob : 1;

	u32	inter_ee_ch_ctrl : 1;

	u32	inter_ee_ev_ctrl : 1;

	u32	general : 1;

	u32	reserved0 : 25;

};

union gsi_hwio_def_ee_n_cntxt_type_irq_u {

	struct gsi_hwio_def_ee_n_cntxt_type_irq_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s {

	u32	ch_ctrl : 1;

	u32	ev_ctrl : 1;

	u32	glob_ee : 1;

	u32	ieob : 1;

	u32	inter_ee_ch_ctrl : 1;

	u32	inter_ee_ev_ctrl : 1;

	u32	general : 1;

	u32	reserved0 : 25;

};

union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u {

	struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s {

	u32 gsi_ch_bit_map : 32;

};

union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_u {

	struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s {

	u32 ev_ch_bit_map : 32;

};

union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_u {

	struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s {

	u32	gsi_ch_bit_map_msk : 23;

	u32	reserved0 : 9;

};

union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_u {

	struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s {

	u32	ev_ch_bit_map_msk : 20;

	u32	reserved0 : 12;

};

union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_u {

	struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s {

	u32 gsi_ch_bit_map : 32;

};

union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_u {

	struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s {

	u32 ev_ch_bit_map : 32;

};

union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_u {

	struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s {

	u32 ev_ch_bit_map : 32;

};

union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_u {

	struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s {

	u32	ev_ch_bit_map_msk : 20;

	u32	reserved0 : 12;

};

union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_u {

	struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s {

	u32 ev_ch_bit_map : 32;

};

union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_u {

	struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s	def;

	u32							value;

};

struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s {

	u32	error_int : 1;

	u32	gp_int1 : 1;

	u32	gp_int2 : 1;

	u32	gp_int3 : 1;

	u32	reserved0 : 28;

};

union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u {

	struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s {

	u32	gsi_break_point : 1;

	u32	gsi_bus_error : 1;

	u32	gsi_cmd_fifo_ovrflow : 1;

	u32	gsi_mcs_stack_ovrflow : 1;

	u32	reserved0 : 28;

};

union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u {

	struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_intset_s {

	u32	intype : 1;

	u32	reserved0 : 31;

};

union gsi_hwio_def_ee_n_cntxt_intset_u {

	struct gsi_hwio_def_ee_n_cntxt_intset_s def;

	u32					value;

};

struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s {

	u32 msi_addr_lsb : 32;

};

union gsi_hwio_def_ee_n_cntxt_msi_base_lsb_u {

	struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s {

	u32 msi_addr_msb : 32;

};

union gsi_hwio_def_ee_n_cntxt_msi_base_msb_u {

	struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_error_log_s {

	u32 error_log : 32;

};

union gsi_hwio_def_ee_n_error_log_u {

	struct gsi_hwio_def_ee_n_error_log_s	def;

	u32					value;

};

struct gsi_hwio_def_ee_n_error_log_clr_s {

	u32 error_log_clr : 32;

};

union gsi_hwio_def_ee_n_error_log_clr_u {

	struct gsi_hwio_def_ee_n_error_log_clr_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_scratch_0_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_cntxt_scratch_0_u {

	struct gsi_hwio_def_ee_n_cntxt_scratch_0_s	def;

	u32						value;

};

struct gsi_hwio_def_ee_n_cntxt_scratch_1_s {

	u32 scratch : 32;

};

union gsi_hwio_def_ee_n_cntxt_scratch_1_u {

	struct gsi_hwio_def_ee_n_cntxt_scratch_1_s	def;

	u32						value;

};

#endif