dt-bindings: ata: add DT bindings for MediaTek SATA controller

MediaTek Serial ATA controller

Required properties:

 - compatible	   : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".

		     When using "mediatek,mtk-ahci" compatible strings, you

		     need SoC specific ones in addition, one of:

		     - "mediatek,mt7622-ahci"

 - reg		   : Physical base addresses and length of register sets.

 - interrupts	   : Interrupt associated with the SATA device.

 - interrupt-names : Associated name must be: "hostc".

 - clocks	   : A list of phandle and clock specifier pairs, one for each

		     entry in clock-names.

 - clock-names	   : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".

 - phys		   : A phandle and PHY specifier pair for the PHY port.

 - phy-names	   : Associated name must be: "sata-phy".

 - ports-implemented : See ./ahci-platform.txt for details.

Optional properties:

 - power-domains   : A phandle and power domain specifier pair to the power

		     domain which is responsible for collapsing and restoring

		     power to the peripheral.

 - resets	   : Must contain an entry for each entry in reset-names.

		     See ../reset/reset.txt for details.

 - reset-names	   : Associated names must be: "axi", "sw", "reg".

 - mediatek,phy-mode : A phandle to the system controller, used to enable

		       SATA function.

Example:

	sata: sata@1a200000 {

		compatible = "mediatek,mt7622-ahci",

			     "mediatek,mtk-ahci";

		reg = <0 0x1a200000 0 0x1100>;

		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hostc";

		clocks = <&pciesys CLK_SATA_AHB_EN>,

			 <&pciesys CLK_SATA_AXI_EN>,

			 <&pciesys CLK_SATA_ASIC_EN>,

			 <&pciesys CLK_SATA_RBC_EN>,

			 <&pciesys CLK_SATA_PM_EN>;

		clock-names = "ahb", "axi", "asic", "rbc", "pm";

		phys = <&u3port1 PHY_TYPE_SATA>;

		phy-names = "sata-phy";

		ports-implemented = <0x1>;

		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;

		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,

			 <&pciesys MT7622_SATA_PHY_SW_RST>,

			 <&pciesys MT7622_SATA_PHY_REG_RST>;

		reset-names = "axi", "sw", "reg";

		mediatek,phy-mode = <&pciesys>;

	};