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Commit 682e77c8 authored by Mahesh Salgaonkar's avatar Mahesh Salgaonkar Committed by Michael Ellerman
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powerpc/book3s: Fix partial invalidation of TLBs in MCE code. 



The existing MCE code calls flush_tlb hook with IS=0 (single page) resulting
in partial invalidation of TLBs which is not right. This patch fixes
that by passing IS=0xc00 to invalidate whole TLB for successful recovery
from TLB and ERAT errors.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarMahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent aefa5688

arch/powerpc/kernel/mce_power.c

+2 −2
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits) 
	}

	if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {

		if (cur_cpu_spec && cur_cpu_spec->flush_tlb)

			cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);

			cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);

		/* reset error bits */

		dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;

	}
@@ -110,7 +110,7 @@ static long mce_handle_common_ierror(uint64_t srr1) 
		break;

	case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:

		if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {

			cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);

			cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);

			handled = 1;

		}

		break;