Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6773f9c1 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: update embedded UFS device related DT properties on Kona"

parents 8843331b a176c21b

arch/arm64/boot/dts/qcom/kona.dtsi

+6 −8
Original line number Original line Diff line number Diff line
@@ -1848,11 +1848,9 @@ 
		lanes-per-direction = <2>;

		lanes-per-direction = <2>;





		clock-names = "ref_clk_src",

		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

			"ref_aux_clk";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_1X_CLKREF_EN>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;





		status = "disabled";

		status = "disabled";

	};

	};
@@ -1879,11 +1877,11 @@ 
			"rx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

			"rx_lane1_sync_clk";

		clocks =

		clocks =

			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>,

			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
@@ -1893,7 +1891,7 @@ 
			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>,

			<37500000 300000000>,

			<37500000 300000000>,

			<75000000 300000000>,

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>,