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Commit 67613f02 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
Browse files

MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction 



MIPS R6 introduced the following instruction:
SELEQZ.fmt: FPR[fd]  FPR[ft].bit0 ? 0 : FPR[fs]

Add support for emulating the single and double precision formats
of the said instruction.

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10954/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent f8c3c671

arch/mips/math-emu/cp1emu.c

+23 −0
Original line number Diff line number Diff line
@@ -1743,6 +1743,17 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			SPFROMREG(rv.s, MIPSInst_FS(ir));

			break;



		case fseleqz_op:

			if (!cpu_has_mips_r6)

				return SIGILL;



			SPFROMREG(rv.s, MIPSInst_FT(ir));

			if (rv.w & 0x1)

				rv.w = 0;

			else

				SPFROMREG(rv.s, MIPSInst_FS(ir));

			break;



		case fabs_op:

			handler.u = ieee754sp_abs;

			goto scopuop;
@@ -1940,6 +1951,18 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
				return 0;

			DPFROMREG(rv.d, MIPSInst_FS(ir));

			break;



		case fseleqz_op:

			if (!cpu_has_mips_r6)

				return SIGILL;



			DPFROMREG(rv.d, MIPSInst_FT(ir));

			if (rv.l & 0x1)

				rv.l = 0;

			else

				DPFROMREG(rv.d, MIPSInst_FS(ir));

			break;



		case fabs_op:

			handler.u = ieee754dp_abs;

			goto dcopuop;