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Commit 67538790 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'tg3-fixes' 



Siva Reddy Kallam says:

====================
tg3: update on copyright and couple of fixes

First patch:
	Update copyright

Second patch:
	Add workaround to restrict 5762 MRRS

Third patch:
	Add PHY reset in change MTU path for 5720
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 65bbbf6c e60ee41a

drivers/net/ethernet/broadcom/tg3.c

+16 −3
Original line number Diff line number Diff line
@@ -4,11 +4,13 @@ 
 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)

 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)

 * Copyright (C) 2004 Sun Microsystems Inc.

 * Copyright (C) 2005-2014 Broadcom Corporation.

 * Copyright (C) 2005-2016 Broadcom Corporation.

 * Copyright (C) 2016-2017 Broadcom Limited.

 *

 * Firmware is:

 *	Derived from proprietary unpublished source code,

 *	Copyright (C) 2000-2003 Broadcom Corporation.

 *	Copyright (C) 2000-2016 Broadcom Corporation.

 *	Copyright (C) 2016-2017 Broadcom Ltd.

 *

 *	Permission is hereby granted for the distribution of this firmware

 *	data in hexadecimal or equivalent format, provided this copyright
@@ -10052,6 +10054,16 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) 


	tw32(GRC_MODE, tp->grc_mode | val);



	/* On one of the AMD platform, MRRS is restricted to 4000 because of

	 * south bridge limitation. As a workaround, Driver is setting MRRS

	 * to 2048 instead of default 4096.

	 */

	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&

	    tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {

		val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;

		tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);

	}



	/* Setup the timer prescalar register.  Clock is always 66Mhz. */

	val = tr32(GRC_MISC_CFG);

	val &= ~0xff;
@@ -14227,7 +14239,8 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu) 
	 */

	if (tg3_asic_rev(tp) == ASIC_REV_57766 ||

	    tg3_asic_rev(tp) == ASIC_REV_5717 ||

	    tg3_asic_rev(tp) == ASIC_REV_5719)

	    tg3_asic_rev(tp) == ASIC_REV_5719 ||

	    tg3_asic_rev(tp) == ASIC_REV_5720)

		reset_phy = true;



	err = tg3_restart_hw(tp, reset_phy);

drivers/net/ethernet/broadcom/tg3.h

+6 −1
Original line number Diff line number Diff line
@@ -5,7 +5,8 @@ 
 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)

 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)

 * Copyright (C) 2004 Sun Microsystems Inc.

 * Copyright (C) 2007-2014 Broadcom Corporation.

 * Copyright (C) 2007-2016 Broadcom Corporation.

 * Copyright (C) 2016-2017 Broadcom Limited.

 */



#ifndef _T3_H
@@ -96,6 +97,7 @@ 
#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR		0x0106

#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT		0x0109

#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT	0x010a

#define TG3PCI_SUBDEVICE_ID_DELL_5762		0x07f0

#define TG3PCI_SUBVENDOR_ID_COMPAQ		PCI_VENDOR_ID_COMPAQ

#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE	0x007c

#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2	0x009a
@@ -281,6 +283,9 @@ 
#define TG3PCI_STD_RING_PROD_IDX	0x00000098 /* 64-bit */

#define TG3PCI_RCV_RET_RING_CON_IDX	0x000000a0 /* 64-bit */

/* 0xa8 --> 0xb8 unused */

#define TG3PCI_DEV_STATUS_CTRL		0x000000b4

#define  MAX_READ_REQ_SIZE_2048		 0x00004000

#define  MAX_READ_REQ_MASK		 0x00007000

#define TG3PCI_DUAL_MAC_CTRL		0x000000b8

#define  DUAL_MAC_CTRL_CH_MASK		 0x00000003

#define  DUAL_MAC_CTRL_ID		 0x00000004