Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 670b90d2 authored by Durgadoss R's avatar Durgadoss R Committed by Daniel Vetter
Browse files

drm/i915: PSR: Keep sink state consistent with source 



BSpec recommends to keep the main link state consistent
between the source and the sink. As per that, update
the main link state in sink DPCD register to 'active',
for Valleyview based platforms.

Signed-off-by: default avatarDurgadoss R <durgadoss.r@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b728d726

drivers/gpu/drm/i915/intel_psr.c

+1 −1
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) 
static void vlv_psr_enable_sink(struct intel_dp *intel_dp)

{

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,

			   DP_PSR_ENABLE);

			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);

}



static void hsw_psr_enable_sink(struct intel_dp *intel_dp)