Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 66478475 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Assorted INTEL_INFO(dev) cleanups 



A bunch of source files with just a few instances of the
incorrect INTEL_INFO use.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 29b74b7f

drivers/gpu/drm/i915/intel_color.c

+2 −3
Original line number Diff line number Diff line
@@ -95,8 +95,7 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input) 
static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)

{

	struct drm_crtc *crtc = crtc_state->crtc;

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(crtc->dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int i, pipe = intel_crtc->pipe;

	uint16_t coeffs[9] = { 0, };
@@ -180,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) 
	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);

	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);



	if (INTEL_INFO(dev)->gen > 6) {

	if (INTEL_GEN(dev_priv) > 6) {

		uint16_t postoff = 0;



		if (intel_crtc_state->limited_color_range)

drivers/gpu/drm/i915/intel_crt.c

+6 −9
Original line number Diff line number Diff line
@@ -147,14 +147,13 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, 
			       struct intel_crtc_state *crtc_state,

			       int mode)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crt *crt = intel_encoder_to_crt(encoder);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;

	u32 adpa;



	if (INTEL_INFO(dev)->gen >= 5)

	if (INTEL_GEN(dev_priv) >= 5)

		adpa = ADPA_HOTPLUG_BITS;

	else

		adpa = 0;
@@ -673,8 +672,7 @@ static const struct dmi_system_id intel_spurious_crt_detect[] = { 
static enum drm_connector_status

intel_crt_detect(struct drm_connector *connector, bool force)

{

	struct drm_device *dev = connector->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(connector->dev);

	struct intel_crt *crt = intel_attached_crt(connector);

	struct intel_encoder *intel_encoder = &crt->base;

	enum intel_display_power_domain power_domain;
@@ -731,7 +729,7 @@ intel_crt_detect(struct drm_connector *connector, bool force) 
	if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {

		if (intel_crt_detect_ddc(connector))

			status = connector_status_connected;

		else if (INTEL_INFO(dev)->gen < 4)

		else if (INTEL_GEN(dev_priv) < 4)

			status = intel_crt_load_detect(crt,

				to_intel_crtc(connector->state->crtc)->pipe);

		else if (i915.load_detect_test)
@@ -793,11 +791,10 @@ static int intel_crt_set_property(struct drm_connector *connector, 


void intel_crt_reset(struct drm_encoder *encoder)

{

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(encoder->dev);

	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));



	if (INTEL_INFO(dev)->gen >= 5) {

	if (INTEL_GEN(dev_priv) >= 5) {

		u32 adpa;



		adpa = I915_READ(crt->adpa_reg);

drivers/gpu/drm/i915/intel_ddi.c

+4 −6
Original line number Diff line number Diff line
@@ -1753,8 +1753,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, 
				   struct drm_connector_state *old_conn_state)

{

	struct drm_encoder *encoder = &intel_encoder->base;

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(encoder->dev);

	enum port port = intel_ddi_get_encoder_port(intel_encoder);

	int type = intel_encoder->type;

	uint32_t val;
@@ -1787,7 +1786,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, 
	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |

					DPLL_CTRL2_DDI_CLK_OFF(port)));

	else if (INTEL_INFO(dev)->gen < 9)

	else if (INTEL_GEN(dev_priv) < 9)

		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);



	if (type == INTEL_OUTPUT_HDMI) {
@@ -1837,8 +1836,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, 
	struct drm_encoder *encoder = &intel_encoder->base;

	struct drm_crtc *crtc = encoder->crtc;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(encoder->dev);

	enum port port = intel_ddi_get_encoder_port(intel_encoder);

	int type = intel_encoder->type;
@@ -1856,7 +1854,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, 
	} else if (type == INTEL_OUTPUT_EDP) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



		if (port == PORT_A && INTEL_INFO(dev)->gen < 9)

		if (port == PORT_A && INTEL_GEN(dev_priv) < 9)

			intel_dp_stop_link_train(intel_dp);



		intel_edp_backlight_on(intel_dp);

drivers/gpu/drm/i915/intel_dpll_mgr.c

+2 −3
Original line number Diff line number Diff line
@@ -188,13 +188,12 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc) 


void intel_disable_shared_dpll(struct intel_crtc *crtc)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_shared_dpll *pll = crtc->config->shared_dpll;

	unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);



	/* PCH only available on ILK+ */

	if (INTEL_INFO(dev)->gen < 5)

	if (INTEL_GEN(dev_priv) < 5)

		return;



	if (pll == NULL)

drivers/gpu/drm/i915/intel_lvds.c

+3 −4
Original line number Diff line number Diff line
@@ -122,8 +122,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 
static void intel_lvds_get_config(struct intel_encoder *encoder,

				  struct intel_crtc_state *pipe_config)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);

	u32 tmp, flags = 0;
@@ -139,12 +138,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, 


	pipe_config->base.adjusted_mode.flags |= flags;



	if (INTEL_INFO(dev)->gen < 5)

	if (INTEL_GEN(dev_priv) < 5)

		pipe_config->gmch_pfit.lvds_border_bits =

			tmp & LVDS_BORDER_ENABLE;



	/* gen2/3 store dither state in pfit control, needs to match */

	if (INTEL_INFO(dev)->gen < 4) {

	if (INTEL_GEN(dev_priv) < 4) {

		tmp = I915_READ(PFIT_CONTROL);



		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;