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Commit 663272db authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gcc-sdm660: Add SDCC1 BCR clocks for SDM660"

parents 65652c2a 80843903

drivers/clk/qcom/gcc-sdm660.c

+2 −0
Original line number Original line Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

// SPDX-License-Identifier: GPL-2.0-only

/*

/*

 * Copyright (c) 2016-2017, 2019-2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2017, 2019-2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.

 */

 */





#include <linux/bitops.h>

#include <linux/bitops.h>
@@ -2679,6 +2680,7 @@ static struct clk_regmap *gcc_660_clocks[] = { 
static const struct qcom_reset_map gcc_660_resets[] = {

static const struct qcom_reset_map gcc_660_resets[] = {

	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },

	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },

	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },

	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },

	[GCC_SDCC1_BCR] = { 0x16000 },

	[GCC_UFS_BCR] = { 0x75000 },

	[GCC_UFS_BCR] = { 0x75000 },

	[GCC_USB3_DP_PHY_BCR] = { 0x50028 },

	[GCC_USB3_DP_PHY_BCR] = { 0x50028 },

	[GCC_USB3_PHY_BCR] = { 0x50020 },

	[GCC_USB3_PHY_BCR] = { 0x50020 },

include/dt-bindings/clock/qcom,gcc-sdm660.h

+2 −0
Original line number Original line Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* SPDX-License-Identifier: GPL-2.0-only */

/*

/*

 * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.

 */

 */





#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H

#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
@@ -195,5 +196,6 @@ 
#define GCC_USB_20_BCR				6

#define GCC_USB_20_BCR				6

#define GCC_USB_30_BCR				7

#define GCC_USB_30_BCR				7

#define GCC_USB_PHY_CFG_AHB2PHY_BCR		8

#define GCC_USB_PHY_CFG_AHB2PHY_BCR		8

#define GCC_SDCC1_BCR				9





#endif
 
#endif