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Commit 65d5665b authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by Mark Brown
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spi: sh-msiof: Update calculation of frequency dividing 



sh-msiof of frequency dividing does not perform the calculation, driver have
to manage setting value in the table. It is not possible to set frequency
dividing value close to the actual data in this way. This changes from
frequency dividing of table management to setting by calculation.
This driver is able to set a value close to the actual data.

Signed-off-by: default avatarNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent c8935ef0

drivers/spi/spi-sh-msiof.c

+16 −20
Original line number Original line Diff line number Diff line
@@ -243,42 +243,38 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 




static struct {

static struct {

	unsigned short div;

	unsigned short div;

	unsigned short scr;

	unsigned short brdv;

} const sh_msiof_spi_clk_table[] = {

} const sh_msiof_spi_div_table[] = {

	{ 1,	SCR_BRPS( 1) | SCR_BRDV_DIV_1 },

	{ 1,	SCR_BRDV_DIV_1 },

	{ 2,	SCR_BRPS( 1) | SCR_BRDV_DIV_2 },

	{ 2,	SCR_BRDV_DIV_2 },

	{ 4,	SCR_BRPS( 1) | SCR_BRDV_DIV_4 },

	{ 4,	SCR_BRDV_DIV_4 },

	{ 8,	SCR_BRPS( 1) | SCR_BRDV_DIV_8 },

	{ 8,	SCR_BRDV_DIV_8 },

	{ 16,	SCR_BRPS( 1) | SCR_BRDV_DIV_16 },

	{ 16,	SCR_BRDV_DIV_16 },

	{ 32,	SCR_BRPS( 1) | SCR_BRDV_DIV_32 },

	{ 32,	SCR_BRDV_DIV_32 },

	{ 64,	SCR_BRPS(32) | SCR_BRDV_DIV_2 },

	{ 128,	SCR_BRPS(32) | SCR_BRDV_DIV_4 },

	{ 256,	SCR_BRPS(32) | SCR_BRDV_DIV_8 },

	{ 512,	SCR_BRPS(32) | SCR_BRDV_DIV_16 },

	{ 1024,	SCR_BRPS(32) | SCR_BRDV_DIV_32 },

};

};





static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,

static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,

				      unsigned long parent_rate, u32 spi_hz)

				      unsigned long parent_rate, u32 spi_hz)

{

{

	unsigned long div = 1024;

	unsigned long div = 1024;

	u32 brps, scr;

	size_t k;

	size_t k;





	if (!WARN_ON(!spi_hz || !parent_rate))

	if (!WARN_ON(!spi_hz || !parent_rate))

		div = DIV_ROUND_UP(parent_rate, spi_hz);

		div = DIV_ROUND_UP(parent_rate, spi_hz);





	/* TODO: make more fine grained */

	for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {



		brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);

	for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {

		if (brps <= 32) /* max of brdv is 32 */

		if (sh_msiof_spi_clk_table[k].div >= div)

			break;

			break;

	}

	}





	k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);

	k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);





	sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);

	scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);

	sh_msiof_write(p, TSCR, scr);

	if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))

	if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))

		sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);

		sh_msiof_write(p, RSCR, scr);

}

}





static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)

static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)