Commit 659e839c authored Jul 06, 2018 by Stephen Boyd

clk-meson into clk-fixes

Pull Amlogic clk driver fixes from Jerome Brunet:

These are two simple fixes, yet the first one is quite important as it
solves boots hangs we've been having when FDIV2 gets disabled. This did
not show up before because this particular clock is heavily used and
only gets disabled for a very short period of time before modules (such
as ethernet or emmc) probe.

- fix boot issue with gxbb and gxl platforms
- fix racalculation error in the clk_audio_divider

* tag 'meson-clk-fixes-4.18-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: audio-divider is one based
  clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL

parents edc6f7e9 7813c14c

drivers/clk/meson/clk-audio-divider.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -51,7 +51,7 @@ static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
		struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk);
		unsigned long divider;

		divider = meson_parm_read(clk->map, &adiv->div);
		divider = meson_parm_read(clk->map, &adiv->div) + 1;

		return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
		}

drivers/clk/meson/gxbb.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -498,6 +498,7 @@ static struct clk_regmap gxbb_fclk_div2 = {
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "fclk_div2_div" },
		.num_parents = 1,
		.flags = CLK_IS_CRITICAL,
		},
		};