Loading Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt 0 → 100644 +32 −0 Original line number Diff line number Diff line == Introduction== LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, that can be shared by multiple clients. Clients here are different cores in the SOC, the idea is to minimize the local caches at the clients and migrate to common pool of memory. Cache memory is divided into partitions called slices which are assigned to clients. Clients can query the slice details, activate and deactivate them. Properties: - compatible: Usage: required Value type: <string> Definition: must be "qcom,kona-llcc" - reg: Usage: required Value Type: <prop-encoded-array> Definition: Start address and the the size of the register regions. - regnames: Usage: required Value Type: <stringlist> Definition: Register region names. Must be "llcc_*" Example: cache-controller@9200000 { compatible = "qcom,kona-llcc"; reg = <0x9200000 0x200000> <0x9600000 0x50000>; reg-names = "llcc_base", "llcc_bcast_base"; }; drivers/soc/qcom/Kconfig +17 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,23 @@ config QCOM_GSBI functions for connecting the underlying serial UART, SPI, and I2C devices to the output pins. config QCOM_LLCC tristate "Qualcomm Technologies, Inc. LLCC driver" depends on ARCH_QCOM help Qualcomm Technologies, Inc. platform specific Last Level Cache Controller(LLCC) driver. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. config QCOM_KONA_LLCC tristate "Qualcomm Technologies, Inc. KONA LLCC driver" depends on QCOM_LLCC help Say yes here to enable the LLCC driver for KONA. This provides data required to configure LLCC so that clients can start using the LLCC slices. config QCOM_MDT_LOADER tristate select QCOM_SCM Loading drivers/soc/qcom/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -15,6 +15,8 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o obj-$(CONFIG_QCOM_KONA_LLCC) += llcc-kona.o obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_SECURE_BUFFER) += secure_buffer.o obj-$(CONFIG_MSM_TZ_SMMU) += msm_tz_smmu.o Loading drivers/soc/qcom/llcc-kona.c 0 → 100644 +93 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/soc/qcom/llcc-qcom.h> /* * SCT entry contains of the following parameters * uid: Unique id for the client's use case * slice_id: llcc slice id for each client * max_cap: The maximum capacity of the cache slice provided in KB * priority: Priority of the client used to select victim line for replacement * fixed_size: Determine of the slice has a fixed capacity * bonus_ways: Bonus ways to be used by any slice, bonus way is used only if * it't not a reserved way. * res_ways: Reserved ways for the cache slice, the reserved ways cannot be used * by any other client than the one its assigned to. * cache_mode: Each slice operates as a cache, this controls the mode of the * slice normal or TCM * probe_target_ways: Determines what ways to probe for access hit. When * configured to 1 only bonus and reseved ways are probed. * when configured to 0 all ways in llcc are probed. * dis_cap_alloc: Disable capacity based allocation for a client * write_scid_en: Bit enables write cache support for a given scid. * retain_on_pc: If this bit is set and client has maitained active vote * then the ways assigned to this client are not flushed on power * collapse. * activate_on_init: Activate the slice immidiately after the SCT is programmed */ #define SCT_ENTRY(uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, wse, rp, a) \ { \ .usecase_id = uid, \ .slice_id = sid, \ .max_cap = mc, \ .priority = p, \ .fixed_size = fs, \ .bonus_ways = bway, \ .res_ways = rway, \ .cache_mode = cmod, \ .probe_target_ways = ptw, \ .dis_cap_alloc = dca, \ .write_scid_en = wse, \ .retain_on_pc = rp, \ .activate_on_init = a, \ } static struct llcc_slice_config kona_data[] = { SCT_ENTRY(LLCC_CPUSS, 1, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1), SCT_ENTRY(LLCC_VIDSC0, 2, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_VOICE, 5, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_AUDIO, 6, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_CMPT, 10, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_GPUHTW, 11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_GPU, 12, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 1, 1, 0), SCT_ENTRY(LLCC_MMUHWT, 13, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), SCT_ENTRY(LLCC_CMPTDMA, 15, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_NPU, 23, 2048, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_WLNHW, 24, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_PIMEM, 25, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_DISPVG, 27, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_CVP, 28, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_WRTCH, 31, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), }; static int kona_qcom_llcc_probe(struct platform_device *pdev) { return qcom_llcc_probe(pdev, kona_data, ARRAY_SIZE(kona_data)); } static const struct of_device_id kona_qcom_llcc_of_match[] = { { .compatible = "qcom,kona-llcc", }, { }, }; static struct platform_driver kona_qcom_llcc_driver = { .driver = { .name = "kona-llcc", .of_match_table = kona_qcom_llcc_of_match, }, .probe = kona_qcom_llcc_probe, }; module_platform_driver(kona_qcom_llcc_driver); MODULE_DESCRIPTION("QCOM kona LLCC driver"); MODULE_LICENSE("GPL v2"); drivers/soc/qcom/llcc-slice.c 0 → 100644 +359 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. */ #include <linux/bitmap.h> #include <linux/bitops.h> #include <linux/device.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mutex.h> #include <linux/of_device.h> #include <linux/regmap.h> #include <linux/slab.h> #include <linux/soc/qcom/llcc-qcom.h> #define ACTIVATE BIT(0) #define DEACTIVATE BIT(1) #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) #define ACT_CTRL_ACT_TRIG BIT(0) #define ACT_CTRL_OPCODE_SHIFT 0x01 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 #define ATTR1_FIXED_SIZE_SHIFT 0x03 #define ATTR1_PRIORITY_SHIFT 0x04 #define ATTR1_MAX_CAP_SHIFT 0x10 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0) #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) #define ATTR0_BONUS_WAYS_SHIFT 0x10 #define LLCC_STATUS_READ_DELAY 100 #define CACHE_LINE_SIZE_SHIFT 6 #define LLCC_COMMON_STATUS0 0x0003000c #define LLCC_LB_CNT_MASK GENMASK(31, 28) #define LLCC_LB_CNT_SHIFT 28 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) #define LLCC_TRP_WRSC_EN 0x21F20 #define LLCC_WRSC_SCID_EN(n) BIT(n) #define BANK_OFFSET_STRIDE 0x80000 static struct llcc_drv_data *drv_data; static const struct regmap_config llcc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .fast_io = true, }; /** * llcc_slice_getd - get llcc slice descriptor * @uid: usecase_id for the client * * A pointer to llcc slice descriptor will be returned on success and * and error pointer is returned on failure */ struct llcc_slice_desc *llcc_slice_getd(u32 uid) { const struct llcc_slice_config *cfg; struct llcc_slice_desc *desc; u32 sz, count; cfg = drv_data->cfg; sz = drv_data->cfg_size; for (count = 0; cfg && count < sz; count++, cfg++) if (cfg->usecase_id == uid) break; if (count == sz || !cfg) return ERR_PTR(-ENODEV); desc = kzalloc(sizeof(*desc), GFP_KERNEL); if (!desc) return ERR_PTR(-ENOMEM); desc->slice_id = cfg->slice_id; desc->slice_size = cfg->max_cap; return desc; } EXPORT_SYMBOL(llcc_slice_getd); /** * llcc_slice_putd - llcc slice descritpor * @desc: Pointer to llcc slice descriptor */ void llcc_slice_putd(struct llcc_slice_desc *desc) { kfree(desc); } EXPORT_SYMBOL(llcc_slice_putd); static int llcc_update_act_ctrl(u32 sid, u32 act_ctrl_reg_val, u32 status) { u32 act_ctrl_reg; u32 status_reg; u32 slice_status; int ret; act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); status_reg = LLCC_TRP_STATUSn(sid); /* Set the ACTIVE trigger */ act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, act_ctrl_reg_val); if (ret) return ret; /* Clear the ACTIVE trigger */ act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, act_ctrl_reg_val); if (ret) return ret; ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, slice_status, !(slice_status & status), 0, LLCC_STATUS_READ_DELAY); return ret; } /** * llcc_slice_activate - Activate the llcc slice * @desc: Pointer to llcc slice descriptor * * A value of zero will be returned on success and a negative errno will * be returned in error cases */ int llcc_slice_activate(struct llcc_slice_desc *desc) { int ret; u32 act_ctrl_val; mutex_lock(&drv_data->lock); if (test_bit(desc->slice_id, drv_data->bitmap)) { mutex_unlock(&drv_data->lock); return 0; } act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, DEACTIVATE); if (ret) { mutex_unlock(&drv_data->lock); return ret; } __set_bit(desc->slice_id, drv_data->bitmap); mutex_unlock(&drv_data->lock); return ret; } EXPORT_SYMBOL(llcc_slice_activate); /** * llcc_slice_deactivate - Deactivate the llcc slice * @desc: Pointer to llcc slice descriptor * * A value of zero will be returned on success and a negative errno will * be returned in error cases */ int llcc_slice_deactivate(struct llcc_slice_desc *desc) { u32 act_ctrl_val; int ret; mutex_lock(&drv_data->lock); if (!test_bit(desc->slice_id, drv_data->bitmap)) { mutex_unlock(&drv_data->lock); return 0; } act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, ACTIVATE); if (ret) { mutex_unlock(&drv_data->lock); return ret; } __clear_bit(desc->slice_id, drv_data->bitmap); mutex_unlock(&drv_data->lock); return ret; } EXPORT_SYMBOL(llcc_slice_deactivate); /** * llcc_get_slice_id - return the slice id * @desc: Pointer to llcc slice descriptor */ int llcc_get_slice_id(struct llcc_slice_desc *desc) { return desc->slice_id; } EXPORT_SYMBOL(llcc_get_slice_id); /** * llcc_get_slice_size - return the slice id * @desc: Pointer to llcc slice descriptor */ size_t llcc_get_slice_size(struct llcc_slice_desc *desc) { return desc->slice_size; } EXPORT_SYMBOL(llcc_get_slice_size); static int qcom_llcc_cfg_program(struct platform_device *pdev) { int i; u32 attr1_cfg; u32 attr0_cfg; u32 attr1_val; u32 attr0_val; u32 max_cap_cacheline; u32 sz; int ret; const struct llcc_slice_config *llcc_table; struct llcc_slice_desc desc; sz = drv_data->cfg_size; llcc_table = drv_data->cfg; for (i = 0; i < sz; i++) { attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); attr1_val = llcc_table[i].cache_mode; attr1_val |= llcc_table[i].probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; attr1_val |= llcc_table[i].fixed_size << ATTR1_FIXED_SIZE_SHIFT; attr1_val |= llcc_table[i].priority << ATTR1_PRIORITY_SHIFT; max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap); /* LLCC instances can vary for each target. * The SW writes to broadcast register which gets propagated * to each llcc instace (llcc0,.. llccN). * Since the size of the memory is divided equally amongst the * llcc instances, we need to configure the max cap accordingly. */ max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK; attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT; ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); if (ret) return ret; ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); if (ret) return ret; if (llcc_table[i].write_scid_en) { ret = regmap_write(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, LLCC_WRSC_SCID_EN(llcc_table[i].slice_id)); if (ret) return ret; } if (llcc_table[i].activate_on_init) { desc.slice_id = llcc_table[i].slice_id; ret = llcc_slice_activate(&desc); if (ret) return ret; } } return 0; } int qcom_llcc_probe(struct platform_device *pdev, const struct llcc_slice_config *llcc_cfg, u32 sz) { u32 num_banks; struct device *dev = &pdev->dev; struct resource *banks_res, *bcast_res; void __iomem *banks_base, *bcast_base; int ret, i; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) return -ENOMEM; banks_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "llcc_base"); banks_base = devm_ioremap_resource(&pdev->dev, banks_res); if (IS_ERR(banks_base)) return PTR_ERR(banks_base); drv_data->regmap = devm_regmap_init_mmio(dev, banks_base, &llcc_regmap_config); if (IS_ERR(drv_data->regmap)) return PTR_ERR(drv_data->regmap); bcast_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "llcc_broadcast_base"); bcast_base = devm_ioremap_resource(&pdev->dev, bcast_res); if (IS_ERR(bcast_base)) return PTR_ERR(bcast_base); drv_data->bcast_regmap = devm_regmap_init_mmio(dev, bcast_base, &llcc_regmap_config); if (IS_ERR(drv_data->bcast_regmap)) return PTR_ERR(drv_data->bcast_regmap); ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, &num_banks); if (ret) return ret; num_banks &= LLCC_LB_CNT_MASK; num_banks >>= LLCC_LB_CNT_SHIFT; drv_data->num_banks = num_banks; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), GFP_KERNEL); if (!drv_data->offsets) return -ENOMEM; for (i = 0; i < num_banks; i++) drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; drv_data->bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), GFP_KERNEL); if (!drv_data->bitmap) return -ENOMEM; drv_data->cfg = llcc_cfg; drv_data->cfg_size = sz; mutex_init(&drv_data->lock); platform_set_drvdata(pdev, drv_data); return qcom_llcc_cfg_program(pdev); } EXPORT_SYMBOL(qcom_llcc_probe); Loading
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt 0 → 100644 +32 −0 Original line number Diff line number Diff line == Introduction== LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, that can be shared by multiple clients. Clients here are different cores in the SOC, the idea is to minimize the local caches at the clients and migrate to common pool of memory. Cache memory is divided into partitions called slices which are assigned to clients. Clients can query the slice details, activate and deactivate them. Properties: - compatible: Usage: required Value type: <string> Definition: must be "qcom,kona-llcc" - reg: Usage: required Value Type: <prop-encoded-array> Definition: Start address and the the size of the register regions. - regnames: Usage: required Value Type: <stringlist> Definition: Register region names. Must be "llcc_*" Example: cache-controller@9200000 { compatible = "qcom,kona-llcc"; reg = <0x9200000 0x200000> <0x9600000 0x50000>; reg-names = "llcc_base", "llcc_bcast_base"; };
drivers/soc/qcom/Kconfig +17 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,23 @@ config QCOM_GSBI functions for connecting the underlying serial UART, SPI, and I2C devices to the output pins. config QCOM_LLCC tristate "Qualcomm Technologies, Inc. LLCC driver" depends on ARCH_QCOM help Qualcomm Technologies, Inc. platform specific Last Level Cache Controller(LLCC) driver. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. config QCOM_KONA_LLCC tristate "Qualcomm Technologies, Inc. KONA LLCC driver" depends on QCOM_LLCC help Say yes here to enable the LLCC driver for KONA. This provides data required to configure LLCC so that clients can start using the LLCC slices. config QCOM_MDT_LOADER tristate select QCOM_SCM Loading
drivers/soc/qcom/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -15,6 +15,8 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o obj-$(CONFIG_QCOM_KONA_LLCC) += llcc-kona.o obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_SECURE_BUFFER) += secure_buffer.o obj-$(CONFIG_MSM_TZ_SMMU) += msm_tz_smmu.o Loading
drivers/soc/qcom/llcc-kona.c 0 → 100644 +93 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/soc/qcom/llcc-qcom.h> /* * SCT entry contains of the following parameters * uid: Unique id for the client's use case * slice_id: llcc slice id for each client * max_cap: The maximum capacity of the cache slice provided in KB * priority: Priority of the client used to select victim line for replacement * fixed_size: Determine of the slice has a fixed capacity * bonus_ways: Bonus ways to be used by any slice, bonus way is used only if * it't not a reserved way. * res_ways: Reserved ways for the cache slice, the reserved ways cannot be used * by any other client than the one its assigned to. * cache_mode: Each slice operates as a cache, this controls the mode of the * slice normal or TCM * probe_target_ways: Determines what ways to probe for access hit. When * configured to 1 only bonus and reseved ways are probed. * when configured to 0 all ways in llcc are probed. * dis_cap_alloc: Disable capacity based allocation for a client * write_scid_en: Bit enables write cache support for a given scid. * retain_on_pc: If this bit is set and client has maitained active vote * then the ways assigned to this client are not flushed on power * collapse. * activate_on_init: Activate the slice immidiately after the SCT is programmed */ #define SCT_ENTRY(uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, wse, rp, a) \ { \ .usecase_id = uid, \ .slice_id = sid, \ .max_cap = mc, \ .priority = p, \ .fixed_size = fs, \ .bonus_ways = bway, \ .res_ways = rway, \ .cache_mode = cmod, \ .probe_target_ways = ptw, \ .dis_cap_alloc = dca, \ .write_scid_en = wse, \ .retain_on_pc = rp, \ .activate_on_init = a, \ } static struct llcc_slice_config kona_data[] = { SCT_ENTRY(LLCC_CPUSS, 1, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1), SCT_ENTRY(LLCC_VIDSC0, 2, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_VOICE, 5, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_AUDIO, 6, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_CMPT, 10, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_GPUHTW, 11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_GPU, 12, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 1, 1, 0), SCT_ENTRY(LLCC_MMUHWT, 13, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), SCT_ENTRY(LLCC_CMPTDMA, 15, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_NPU, 23, 2048, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_WLNHW, 24, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_PIMEM, 25, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_DISPVG, 27, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_CVP, 28, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_WRTCH, 31, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), }; static int kona_qcom_llcc_probe(struct platform_device *pdev) { return qcom_llcc_probe(pdev, kona_data, ARRAY_SIZE(kona_data)); } static const struct of_device_id kona_qcom_llcc_of_match[] = { { .compatible = "qcom,kona-llcc", }, { }, }; static struct platform_driver kona_qcom_llcc_driver = { .driver = { .name = "kona-llcc", .of_match_table = kona_qcom_llcc_of_match, }, .probe = kona_qcom_llcc_probe, }; module_platform_driver(kona_qcom_llcc_driver); MODULE_DESCRIPTION("QCOM kona LLCC driver"); MODULE_LICENSE("GPL v2");
drivers/soc/qcom/llcc-slice.c 0 → 100644 +359 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. */ #include <linux/bitmap.h> #include <linux/bitops.h> #include <linux/device.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mutex.h> #include <linux/of_device.h> #include <linux/regmap.h> #include <linux/slab.h> #include <linux/soc/qcom/llcc-qcom.h> #define ACTIVATE BIT(0) #define DEACTIVATE BIT(1) #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) #define ACT_CTRL_ACT_TRIG BIT(0) #define ACT_CTRL_OPCODE_SHIFT 0x01 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 #define ATTR1_FIXED_SIZE_SHIFT 0x03 #define ATTR1_PRIORITY_SHIFT 0x04 #define ATTR1_MAX_CAP_SHIFT 0x10 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0) #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) #define ATTR0_BONUS_WAYS_SHIFT 0x10 #define LLCC_STATUS_READ_DELAY 100 #define CACHE_LINE_SIZE_SHIFT 6 #define LLCC_COMMON_STATUS0 0x0003000c #define LLCC_LB_CNT_MASK GENMASK(31, 28) #define LLCC_LB_CNT_SHIFT 28 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) #define LLCC_TRP_WRSC_EN 0x21F20 #define LLCC_WRSC_SCID_EN(n) BIT(n) #define BANK_OFFSET_STRIDE 0x80000 static struct llcc_drv_data *drv_data; static const struct regmap_config llcc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .fast_io = true, }; /** * llcc_slice_getd - get llcc slice descriptor * @uid: usecase_id for the client * * A pointer to llcc slice descriptor will be returned on success and * and error pointer is returned on failure */ struct llcc_slice_desc *llcc_slice_getd(u32 uid) { const struct llcc_slice_config *cfg; struct llcc_slice_desc *desc; u32 sz, count; cfg = drv_data->cfg; sz = drv_data->cfg_size; for (count = 0; cfg && count < sz; count++, cfg++) if (cfg->usecase_id == uid) break; if (count == sz || !cfg) return ERR_PTR(-ENODEV); desc = kzalloc(sizeof(*desc), GFP_KERNEL); if (!desc) return ERR_PTR(-ENOMEM); desc->slice_id = cfg->slice_id; desc->slice_size = cfg->max_cap; return desc; } EXPORT_SYMBOL(llcc_slice_getd); /** * llcc_slice_putd - llcc slice descritpor * @desc: Pointer to llcc slice descriptor */ void llcc_slice_putd(struct llcc_slice_desc *desc) { kfree(desc); } EXPORT_SYMBOL(llcc_slice_putd); static int llcc_update_act_ctrl(u32 sid, u32 act_ctrl_reg_val, u32 status) { u32 act_ctrl_reg; u32 status_reg; u32 slice_status; int ret; act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); status_reg = LLCC_TRP_STATUSn(sid); /* Set the ACTIVE trigger */ act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, act_ctrl_reg_val); if (ret) return ret; /* Clear the ACTIVE trigger */ act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, act_ctrl_reg_val); if (ret) return ret; ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, slice_status, !(slice_status & status), 0, LLCC_STATUS_READ_DELAY); return ret; } /** * llcc_slice_activate - Activate the llcc slice * @desc: Pointer to llcc slice descriptor * * A value of zero will be returned on success and a negative errno will * be returned in error cases */ int llcc_slice_activate(struct llcc_slice_desc *desc) { int ret; u32 act_ctrl_val; mutex_lock(&drv_data->lock); if (test_bit(desc->slice_id, drv_data->bitmap)) { mutex_unlock(&drv_data->lock); return 0; } act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, DEACTIVATE); if (ret) { mutex_unlock(&drv_data->lock); return ret; } __set_bit(desc->slice_id, drv_data->bitmap); mutex_unlock(&drv_data->lock); return ret; } EXPORT_SYMBOL(llcc_slice_activate); /** * llcc_slice_deactivate - Deactivate the llcc slice * @desc: Pointer to llcc slice descriptor * * A value of zero will be returned on success and a negative errno will * be returned in error cases */ int llcc_slice_deactivate(struct llcc_slice_desc *desc) { u32 act_ctrl_val; int ret; mutex_lock(&drv_data->lock); if (!test_bit(desc->slice_id, drv_data->bitmap)) { mutex_unlock(&drv_data->lock); return 0; } act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, ACTIVATE); if (ret) { mutex_unlock(&drv_data->lock); return ret; } __clear_bit(desc->slice_id, drv_data->bitmap); mutex_unlock(&drv_data->lock); return ret; } EXPORT_SYMBOL(llcc_slice_deactivate); /** * llcc_get_slice_id - return the slice id * @desc: Pointer to llcc slice descriptor */ int llcc_get_slice_id(struct llcc_slice_desc *desc) { return desc->slice_id; } EXPORT_SYMBOL(llcc_get_slice_id); /** * llcc_get_slice_size - return the slice id * @desc: Pointer to llcc slice descriptor */ size_t llcc_get_slice_size(struct llcc_slice_desc *desc) { return desc->slice_size; } EXPORT_SYMBOL(llcc_get_slice_size); static int qcom_llcc_cfg_program(struct platform_device *pdev) { int i; u32 attr1_cfg; u32 attr0_cfg; u32 attr1_val; u32 attr0_val; u32 max_cap_cacheline; u32 sz; int ret; const struct llcc_slice_config *llcc_table; struct llcc_slice_desc desc; sz = drv_data->cfg_size; llcc_table = drv_data->cfg; for (i = 0; i < sz; i++) { attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); attr1_val = llcc_table[i].cache_mode; attr1_val |= llcc_table[i].probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; attr1_val |= llcc_table[i].fixed_size << ATTR1_FIXED_SIZE_SHIFT; attr1_val |= llcc_table[i].priority << ATTR1_PRIORITY_SHIFT; max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap); /* LLCC instances can vary for each target. * The SW writes to broadcast register which gets propagated * to each llcc instace (llcc0,.. llccN). * Since the size of the memory is divided equally amongst the * llcc instances, we need to configure the max cap accordingly. */ max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK; attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT; ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); if (ret) return ret; ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); if (ret) return ret; if (llcc_table[i].write_scid_en) { ret = regmap_write(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, LLCC_WRSC_SCID_EN(llcc_table[i].slice_id)); if (ret) return ret; } if (llcc_table[i].activate_on_init) { desc.slice_id = llcc_table[i].slice_id; ret = llcc_slice_activate(&desc); if (ret) return ret; } } return 0; } int qcom_llcc_probe(struct platform_device *pdev, const struct llcc_slice_config *llcc_cfg, u32 sz) { u32 num_banks; struct device *dev = &pdev->dev; struct resource *banks_res, *bcast_res; void __iomem *banks_base, *bcast_base; int ret, i; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) return -ENOMEM; banks_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "llcc_base"); banks_base = devm_ioremap_resource(&pdev->dev, banks_res); if (IS_ERR(banks_base)) return PTR_ERR(banks_base); drv_data->regmap = devm_regmap_init_mmio(dev, banks_base, &llcc_regmap_config); if (IS_ERR(drv_data->regmap)) return PTR_ERR(drv_data->regmap); bcast_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "llcc_broadcast_base"); bcast_base = devm_ioremap_resource(&pdev->dev, bcast_res); if (IS_ERR(bcast_base)) return PTR_ERR(bcast_base); drv_data->bcast_regmap = devm_regmap_init_mmio(dev, bcast_base, &llcc_regmap_config); if (IS_ERR(drv_data->bcast_regmap)) return PTR_ERR(drv_data->bcast_regmap); ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, &num_banks); if (ret) return ret; num_banks &= LLCC_LB_CNT_MASK; num_banks >>= LLCC_LB_CNT_SHIFT; drv_data->num_banks = num_banks; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), GFP_KERNEL); if (!drv_data->offsets) return -ENOMEM; for (i = 0; i < num_banks; i++) drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; drv_data->bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), GFP_KERNEL); if (!drv_data->bitmap) return -ENOMEM; drv_data->cfg = llcc_cfg; drv_data->cfg_size = sz; mutex_init(&drv_data->lock); platform_set_drvdata(pdev, drv_data); return qcom_llcc_cfg_program(pdev); } EXPORT_SYMBOL(qcom_llcc_probe);
