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Commit 65390ea0 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
Browse files

Merge branch 'patchwork' into v4l_for_linus 

* patchwork: (496 commits)
  [media] v4l: tvp5150: Add missing break in set control handler
  [media] v4l: tvp5150: Don't inline the tvp5150_selmux() function
  [media] v4l: tvp5150: Compile tvp5150_link_setup out if !CONFIG_MEDIA_CONTROLLER
  [media] em28xx: don't store usb_device at struct em28xx
  [media] em28xx: use usb_interface for dev_foo() calls
  [media] em28xx: don't change the device's name
  [media] mn88472: fix chip id check on probe
  [media] mn88473: fix chip id check on probe
  [media] lirc: fix error paths in lirc_cdev_add()
  [media] s5p-mfc: Add support for MFC v8 available in Exynos 5433 SoCs
  [media] s5p-mfc: Rework clock handling
  [media] s5p-mfc: Don't keep clock prepared all the time
  [media] s5p-mfc: Kill all IS_ERR_OR_NULL in clocks management code
  [media] s5p-mfc: Remove dead conditional code
  [media] s5p-mfc: Ensure that clock is disabled before turning power off
  [media] s5p-mfc: Remove special clock rate management
  [media] s5p-mfc: Use printk_ratelimited for reporting ioctl errors
  [media] s5p-mfc: Set DMA_ATTR_ALLOC_SINGLE_PAGES
  [media] vivid: Set color_enc on HSV formats
  [media] v4l2-tpg: Init hv_enc field with a valid value
  ...
parents e7aa8c2e d183e4ef

Documentation/devicetree/bindings/media/exynos5-gsc.txt

+2 −1
Original line number Diff line number Diff line
@@ -3,7 +3,8 @@ 
G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs.



Required properties:

- compatible: should be "samsung,exynos5-gsc"

- compatible: should be "samsung,exynos5-gsc" (for Exynos 5250, 5420 and

	      5422 SoCs) or "samsung,exynos5433-gsc" (Exynos 5433)

- reg: should contain G-Scaler physical address location and length.

- interrupts: should contain G-Scaler interrupt number

Documentation/devicetree/bindings/media/hix5hd2-ir.txt

+3 −3
Original line number Diff line number Diff line
@@ -8,10 +8,11 @@ Required properties: 
	  the device. The interrupt specifier format depends on the interrupt

	  controller parent.

	- clocks: clock phandle and specifier pair.

	- hisilicon,power-syscon: phandle of syscon used to control power.



Optional properties:

	- linux,rc-map-name : Remote control map name.

	- hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.

		Provide correct clocks instead.



Example node:
@@ -19,7 +20,6 @@ Example node: 
		compatible = "hisilicon,hix5hd2-ir";

		reg = <0xf8001000 0x1000>;

		interrupts = <0 47 4>;

		clocks = <&clock HIX5HD2_FIXED_24M>;

		hisilicon,power-syscon = <&sysctrl>;

		clocks = <&clock HIX5HD2_IR_CLOCK>;

		linux,rc-map-name = "rc-tivo";

	};

Documentation/devicetree/bindings/media/i2c/adv7604.txt

+1 −2
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ The digital output port node must contain at least one endpoint. 
Optional Properties:



  - reset-gpios: Reference to the GPIO connected to the device's reset pin.

  - default-input: Select which input is selected after reset.



Optional Endpoint Properties:
@@ -47,8 +48,6 @@ Optional Endpoint Properties: 
  If none of hsync-active, vsync-active and pclk-sample is specified the

  endpoint will use embedded BT.656 synchronization.



  - default-input: Select which input is selected after reset.



Example:



	hdmi_receiver@4c {

Documentation/devicetree/bindings/media/mediatek-mdp.txt

0 → 100644
+109 −0
Original line number Diff line number Diff line 
* Mediatek Media Data Path



Media Data Path is used for scaling and color space conversion.



Required properties (controller (parent) node):

- compatible: "mediatek,mt8173-mdp"

- mediatek,vpu: the node of video processor unit, see

  Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.



Required properties (all function blocks, child node):

- compatible: Should be one of

        "mediatek,mt8173-mdp-rdma"  - read DMA

        "mediatek,mt8173-mdp-rsz"   - resizer

        "mediatek,mt8173-mdp-wdma"  - write DMA

        "mediatek,mt8173-mdp-wrot"  - write DMA with rotation

- reg: Physical base address and length of the function block register space

- clocks: device clocks, see

  Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- power-domains: a phandle to the power domain, see

  Documentation/devicetree/bindings/power/power_domain.txt for details.



Required properties (DMA function blocks, child node):

- compatible: Should be one of

        "mediatek,mt8173-mdp-rdma"

        "mediatek,mt8173-mdp-wdma"

        "mediatek,mt8173-mdp-wrot"

- iommus: should point to the respective IOMMU block with master port as

  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

  for details.

- mediatek,larb: must contain the local arbiters in the current Socs, see

  Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt

  for details.



Example:

mdp {

	compatible = "mediatek,mt8173-mdp";

	#address-cells = <2>;

	#size-cells = <2>;

	ranges;

	mediatek,vpu = <&vpu>;



	mdp_rdma0: rdma@14001000 {

		compatible = "mediatek,mt8173-mdp-rdma";

		reg = <0 0x14001000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RDMA0>,

			 <&mmsys CLK_MM_MUTEX_32K>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_RDMA0>;

		mediatek,larb = <&larb0>;

	};



	mdp_rdma1: rdma@14002000 {

		compatible = "mediatek,mt8173-mdp-rdma";

		reg = <0 0x14002000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RDMA1>,

			 <&mmsys CLK_MM_MUTEX_32K>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_RDMA1>;

		mediatek,larb = <&larb4>;

	};



	mdp_rsz0: rsz@14003000 {

		compatible = "mediatek,mt8173-mdp-rsz";

		reg = <0 0x14003000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RSZ0>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	};



	mdp_rsz1: rsz@14004000 {

		compatible = "mediatek,mt8173-mdp-rsz";

		reg = <0 0x14004000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RSZ1>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	};



	mdp_rsz2: rsz@14005000 {

		compatible = "mediatek,mt8173-mdp-rsz";

		reg = <0 0x14005000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RSZ2>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	};



	mdp_wdma0: wdma@14006000 {

		compatible = "mediatek,mt8173-mdp-wdma";

		reg = <0 0x14006000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_WDMA>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_WDMA>;

		mediatek,larb = <&larb0>;

	};



	mdp_wrot0: wrot@14007000 {

		compatible = "mediatek,mt8173-mdp-wrot";

		reg = <0 0x14007000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_WROT0>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_WROT0>;

		mediatek,larb = <&larb0>;

	};



	mdp_wrot1: wrot@14008000 {

		compatible = "mediatek,mt8173-mdp-wrot";

		reg = <0 0x14008000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_WROT1>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_WROT1>;

		mediatek,larb = <&larb4>;

	};

};

Documentation/devicetree/bindings/media/mediatek-vcodec.txt

+53 −4
Original line number Diff line number Diff line 
Mediatek Video Codec



Mediatek Video Codec is the video codec hw present in Mediatek SoCs which

supports high resolution encoding functionalities.

supports high resolution encoding and decoding functionalities.



Required properties:

- compatible : "mediatek,mt8173-vcodec-enc" for encoder

  "mediatek,mt8173-vcodec-dec" for decoder.

- reg : Physical base address of the video codec registers and length of

  memory mapped region.

- interrupts : interrupt number to the cpu.

- mediatek,larb : must contain the local arbiters in the current Socs.

- clocks : list of clock specifiers, corresponding to entries in

  the clock-names property.

- clock-names: encoder must contain "venc_sel_src", "venc_sel",

- "venc_lt_sel_src", "venc_lt_sel".

- clock-names: encoder must contain "venc_sel_src", "venc_sel",,

  "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",

  "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",

  "venc_lt_sel", "vdec_bus_clk_src".

- iommus : should point to the respective IOMMU block with master port as

  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

  for details.

- mediatek,vpu : the node of video processor unit





Example:



vcodec_dec: vcodec@16000000 {

    compatible = "mediatek,mt8173-vcodec-dec";

    reg = <0 0x16000000 0 0x100>,   /*VDEC_SYS*/

          <0 0x16020000 0 0x1000>,  /*VDEC_MISC*/

          <0 0x16021000 0 0x800>,   /*VDEC_LD*/

          <0 0x16021800 0 0x800>,   /*VDEC_TOP*/

          <0 0x16022000 0 0x1000>,  /*VDEC_CM*/

          <0 0x16023000 0 0x1000>,  /*VDEC_AD*/

          <0 0x16024000 0 0x1000>,  /*VDEC_AV*/

          <0 0x16025000 0 0x1000>,  /*VDEC_PP*/

          <0 0x16026800 0 0x800>,   /*VP8_VD*/

          <0 0x16027000 0 0x800>,   /*VP6_VD*/

          <0 0x16027800 0 0x800>,   /*VP8_VL*/

          <0 0x16028400 0 0x400>;   /*VP9_VD*/

    interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;

    mediatek,larb = <&larb1>;

    iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,

             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,

             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,

             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,

             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,

             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,

             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,

             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;

    mediatek,vpu = <&vpu>;

    power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;

    clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,

             <&topckgen CLK_TOP_UNIVPLL_D2>,

             <&topckgen CLK_TOP_CCI400_SEL>,

             <&topckgen CLK_TOP_VDEC_SEL>,

             <&topckgen CLK_TOP_VCODECPLL>,

             <&apmixedsys CLK_APMIXED_VENCPLL>,

             <&topckgen CLK_TOP_VENC_LT_SEL>,

             <&topckgen CLK_TOP_VCODECPLL_370P5>;

    clock-names = "vcodecpll",

                  "univpll_d2",

                  "clk_cci400_sel",

                  "vdec_sel",

                  "vdecpll",

                  "vencpll",

                  "venc_lt_sel",

                  "vdec_bus_clk_src";

  };



  vcodec_enc: vcodec@0x18002000 {

    compatible = "mediatek,mt8173-vcodec-enc";

    reg = <0 0x18002000 0 0x1000>,    /*VENC_SYS*/