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Commit 6512387a authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
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drm/amd/display: align DCLK to voltage level 



in past program SMU will use all voltage headroom.  RV does not

if DAL need higher voltage for DCFCLK or DISPCLK, also increase FCLK
to improve stutter as voltage is already

Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 87401969

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+4 −0
Original line number Diff line number Diff line
@@ -1049,6 +1049,10 @@ bool dcn_validate_bandwidth( 
		else

			bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;



		if (bw_consumed < v->fabric_and_dram_bandwidth)

			if (dc->debug.voltage_align_fclk)

				bw_consumed = v->fabric_and_dram_bandwidth;



		display_pipe_configuration(v);

		calc_wm_sets_and_perf_params(context, v);

		context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -188,6 +188,7 @@ struct dc_debug { 
	enum dcc_option disable_dcc;

	enum pipe_split_policy pipe_split_policy;

	bool force_single_disp_pipe_split;

	bool voltage_align_fclk;



	bool disable_dfs_bypass;

	bool disable_dpp_power_gate;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -428,6 +428,7 @@ static const struct dc_debug debug_defaults_drv = { 


		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,

		.disable_dcc = DCC_ENABLE,

		.voltage_align_fclk = true,

};



static const struct dc_debug debug_defaults_diags = {