Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 650dc07e authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: disable ppgtt on snb when dmar is enabled 



Totally unexpected that this regressed. Luckily it sounds like we just
need to have dmar disable on the igfx, not the entire system. At least
that's what a few days of testing between Tony Vroon and me indicates.

Reported-by: default avatarTony Vroon <tony@linx.net>
Cc: Tony Vroon <tony@linx.net>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43024


Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent cc22a938

drivers/char/agp/intel-gtt.c

+0 −1
Original line number Diff line number Diff line
@@ -1190,7 +1190,6 @@ static inline int needs_idle_maps(void) 
{

#ifdef CONFIG_INTEL_IOMMU

	const unsigned short gpu_devid = intel_private.pcidev->device;

	extern int intel_iommu_gfx_mapped;



	/* Query intel_iommu to see if we need the workaround. Presumably that

	 * was loaded first.

drivers/gpu/drm/i915/i915_dma.c

+16 −1
Original line number Diff line number Diff line
@@ -1183,6 +1183,21 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev) 
	return can_switch;

}



static bool

intel_enable_ppgtt(struct drm_device *dev)

{

	if (i915_enable_ppgtt >= 0)

		return i915_enable_ppgtt;



#ifdef CONFIG_INTEL_IOMMU

	/* Disable ppgtt on SNB if VT-d is on. */

	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)

		return false;

#endif



	return true;

}



static int i915_load_gem_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1197,7 +1212,7 @@ static int i915_load_gem_init(struct drm_device *dev) 
	drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);



	mutex_lock(&dev->struct_mutex);

	if (i915_enable_ppgtt && HAS_ALIASING_PPGTT(dev)) {

	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {

		/* PPGTT pdes are stolen from global gtt ptes, so shrink the

		 * aperture accordingly when using aliasing ppgtt. */

		gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -107,8 +107,8 @@ MODULE_PARM_DESC(enable_hangcheck, 
		"WARNING: Disabling this can cause system wide hangs. "

		"(default: true)");



bool i915_enable_ppgtt __read_mostly = 1;

module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);

int i915_enable_ppgtt __read_mostly = -1;

module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);

MODULE_PARM_DESC(i915_enable_ppgtt,

		"Enable PPGTT (default: true)");

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1086,7 +1086,7 @@ extern int i915_vbt_sdvo_panel_type __read_mostly; 
extern int i915_enable_rc6 __read_mostly;

extern int i915_enable_fbc __read_mostly;

extern bool i915_enable_hangcheck __read_mostly;

extern bool i915_enable_ppgtt __read_mostly;

extern int i915_enable_ppgtt __read_mostly;



extern int i915_suspend(struct drm_device *dev, pm_message_t state);

extern int i915_resume(struct drm_device *dev);

include/drm/intel-gtt.h

+4 −0
Original line number Diff line number Diff line
@@ -44,4 +44,8 @@ void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, 
/* flag for GFDT type */

#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)



#ifdef CONFIG_INTEL_IOMMU

extern int intel_iommu_gfx_mapped;

#endif



#endif