Loading Documentation/ABI/testing/sysfs-devices-system-cpu +1 −1 Original line number Diff line number Diff line Loading @@ -162,7 +162,7 @@ Description: Discover CPUs in the same CPU frequency coordination domain What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 KernelVersion: 2.6.27 Contact: discuss@x86-64.org Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> Description: Disable L3 cache indices These files exist in every CPU's cache/index3 directory. Each Loading Documentation/devicetree/bindings/clock/silabs,si5351.txt +3 −1 Original line number Diff line number Diff line Loading @@ -17,7 +17,8 @@ Required properties: - #clock-cells: from common clock binding; shall be set to 1. - clocks: from common clock binding; list of parent clock handles, shall be xtal reference clock or xtal and clkin for si5351c only. si5351c only. Corresponding clock input names are "xtal" and "clkin" respectively. - #address-cells: shall be set to 1. - #size-cells: shall be set to 0. Loading Loading @@ -71,6 +72,7 @@ i2c-master-node { /* connect xtal input to 25MHz reference */ clocks = <&ref25>; clock-names = "xtal"; /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; Loading Documentation/devicetree/bindings/mtd/m25p80.txt→Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +3 −3 Original line number Diff line number Diff line Loading @@ -8,8 +8,8 @@ Required properties: is not Linux-only, but in case of Linux, see the "m25p_ids" table in drivers/mtd/devices/m25p80.c for the list of supported chips. Must also include "nor-jedec" for any SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). Must also include "jedec,spi-nor" for any SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). - reg : Chip-Select number - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at Loading @@ -25,7 +25,7 @@ Example: flash: m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,m25p80", "nor-jedec"; compatible = "spansion,m25p80", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; m25p,fast-read; Loading Documentation/devicetree/bindings/net/cdns-emac.txt +2 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,8 @@ Required properties: - compatible: Should be "cdns,[<chip>-]{emac}" Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. or the generic form: "cdns,emac". Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: see ethernet.txt file in the same directory. Loading Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt 0 → 100644 +10 −0 Original line number Diff line number Diff line * ARM SBSA defined generic UART This UART uses a subset of the PL011 registers and consequently lives in the PL011 driver. It's baudrate and other communication parameters cannot be adjusted at runtime, so it lacks a clock specifier here. Required properties: - compatible: must be "arm,sbsa-uart" - reg: exactly one register range - interrupts: exactly one interrupt specifier - current-speed: the (fixed) baud rate set by the firmware Loading
Documentation/ABI/testing/sysfs-devices-system-cpu +1 −1 Original line number Diff line number Diff line Loading @@ -162,7 +162,7 @@ Description: Discover CPUs in the same CPU frequency coordination domain What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 KernelVersion: 2.6.27 Contact: discuss@x86-64.org Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> Description: Disable L3 cache indices These files exist in every CPU's cache/index3 directory. Each Loading
Documentation/devicetree/bindings/clock/silabs,si5351.txt +3 −1 Original line number Diff line number Diff line Loading @@ -17,7 +17,8 @@ Required properties: - #clock-cells: from common clock binding; shall be set to 1. - clocks: from common clock binding; list of parent clock handles, shall be xtal reference clock or xtal and clkin for si5351c only. si5351c only. Corresponding clock input names are "xtal" and "clkin" respectively. - #address-cells: shall be set to 1. - #size-cells: shall be set to 0. Loading Loading @@ -71,6 +72,7 @@ i2c-master-node { /* connect xtal input to 25MHz reference */ clocks = <&ref25>; clock-names = "xtal"; /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; Loading
Documentation/devicetree/bindings/mtd/m25p80.txt→Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +3 −3 Original line number Diff line number Diff line Loading @@ -8,8 +8,8 @@ Required properties: is not Linux-only, but in case of Linux, see the "m25p_ids" table in drivers/mtd/devices/m25p80.c for the list of supported chips. Must also include "nor-jedec" for any SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). Must also include "jedec,spi-nor" for any SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). - reg : Chip-Select number - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at Loading @@ -25,7 +25,7 @@ Example: flash: m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,m25p80", "nor-jedec"; compatible = "spansion,m25p80", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; m25p,fast-read; Loading
Documentation/devicetree/bindings/net/cdns-emac.txt +2 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,8 @@ Required properties: - compatible: Should be "cdns,[<chip>-]{emac}" Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. or the generic form: "cdns,emac". Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: see ethernet.txt file in the same directory. Loading
Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt 0 → 100644 +10 −0 Original line number Diff line number Diff line * ARM SBSA defined generic UART This UART uses a subset of the PL011 registers and consequently lives in the PL011 driver. It's baudrate and other communication parameters cannot be adjusted at runtime, so it lacks a clock specifier here. Required properties: - compatible: must be "arm,sbsa-uart" - reg: exactly one register range - interrupts: exactly one interrupt specifier - current-speed: the (fixed) baud rate set by the firmware
