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Commit 63863d43 authored by Lucas Stach's avatar Lucas Stach Committed by Philipp Zabel
Browse files

gpu: ipu-v3: add DT binding for the Prefetch Resolve Gasket 



This adds the the devicetree binding for the Prefetch Resolve Gasket,
as found on i.MX6 QuadPlus.
The PRG is fairly simple in that it only has a configuration register
range and two clocks, one for the AHB slave port and one for the AXI
ports and the functional units.

The PRE connections need to be described in the DT, as the PRE<->PRG
assignment is a mix between fixed and muxable connections.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent d2a34232

Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt

+25 −0
Original line number Diff line number Diff line
@@ -79,6 +79,31 @@ pre@21c8000 { 
	fsl,iram = <&ocram2>;

};



Freescale i.MX PRG (Prefetch Resolve Gasket)

============================================



Required properties:

- compatible: should be "fsl,imx6qp-prg"

- reg: should be register base and length as documented in the

  datasheet

- clocks : phandles to the PRG ipg and axi clock inputs, as described

  in Documentation/devicetree/bindings/clock/clock-bindings.txt and

  Documentation/devicetree/bindings/clock/imx6q-clock.txt.

- clock-names: should be "ipg" and "axi"

- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed

  PRE as the first entry and the muxable PREs following.



example:



prg@21cc000 {

	compatible = "fsl,imx6qp-prg";

	reg = <0x021cc000 0x1000>;

	clocks = <&clks IMX6QDL_CLK_PRG0_APB>,

		 <&clks IMX6QDL_CLK_PRG0_AXI>;

	clock-names = "ipg", "axi";

	fsl,pres = <&pre1>, <&pre2>, <&pre3>;

};



Parallel display support

========================