Loading drivers/tty/serial/msm_geni_serial.c +0 −7 Original line number Diff line number Diff line Loading @@ -2335,7 +2335,6 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, * it else we could end up in data loss scenarios. */ msm_geni_serial_poll_cancel_tx(uport); msm_geni_serial_abort_rx(uport); se_get_packing_config(8, 1, false, &cfg0, &cfg1); geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1), Loading @@ -2347,14 +2346,8 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, SE_UART_TX_TRANS_CFG); geni_write_reg_nolog(tx_parity_cfg, uport->membase, SE_UART_TX_PARITY_CFG); geni_write_reg_nolog(rx_trans_cfg, uport->membase, SE_UART_RX_TRANS_CFG); geni_write_reg_nolog(rx_parity_cfg, uport->membase, SE_UART_RX_PARITY_CFG); geni_write_reg_nolog(bits_per_char, uport->membase, SE_UART_TX_WORD_LEN); geni_write_reg_nolog(bits_per_char, uport->membase, SE_UART_RX_WORD_LEN); geni_write_reg_nolog(stop_bit, uport->membase, SE_UART_TX_STOP_BIT_LEN); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG); Loading Loading
drivers/tty/serial/msm_geni_serial.c +0 −7 Original line number Diff line number Diff line Loading @@ -2335,7 +2335,6 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, * it else we could end up in data loss scenarios. */ msm_geni_serial_poll_cancel_tx(uport); msm_geni_serial_abort_rx(uport); se_get_packing_config(8, 1, false, &cfg0, &cfg1); geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1), Loading @@ -2347,14 +2346,8 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, SE_UART_TX_TRANS_CFG); geni_write_reg_nolog(tx_parity_cfg, uport->membase, SE_UART_TX_PARITY_CFG); geni_write_reg_nolog(rx_trans_cfg, uport->membase, SE_UART_RX_TRANS_CFG); geni_write_reg_nolog(rx_parity_cfg, uport->membase, SE_UART_RX_PARITY_CFG); geni_write_reg_nolog(bits_per_char, uport->membase, SE_UART_TX_WORD_LEN); geni_write_reg_nolog(bits_per_char, uport->membase, SE_UART_RX_WORD_LEN); geni_write_reg_nolog(stop_bit, uport->membase, SE_UART_TX_STOP_BIT_LEN); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG); Loading