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Commit 63582983 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915: Correctly prefix HSW/BDW HDMI clock functions 



Those functions were the only one in existence when they were
introduced. We now know they are only valid for HSW/BDW.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 64311571

drivers/gpu/drm/i915/intel_ddi.c

+12 −13
Original line number Original line Diff line number Diff line
@@ -625,11 +625,11 @@ intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 
	(void) (&__a == &__b);			\

	(void) (&__a == &__b);			\

	__a > __b ? (__a - __b) : (__b - __a); })

	__a > __b ? (__a - __b) : (__b - __a); })





struct wrpll_rnp {

struct hsw_wrpll_rnp {

	unsigned p, n2, r2;

	unsigned p, n2, r2;

};

};





static unsigned wrpll_get_budget_for_freq(int clock)

static unsigned hsw_wrpll_get_budget_for_freq(int clock)

{

{

	unsigned budget;

	unsigned budget;
@@ -703,9 +703,9 @@ static unsigned wrpll_get_budget_for_freq(int clock) 
	return budget;

	return budget;

}

}





static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,

static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,

				 unsigned r2, unsigned n2, unsigned p,

				 unsigned r2, unsigned n2, unsigned p,

			     struct wrpll_rnp *best)

				 struct hsw_wrpll_rnp *best)

{

{

	uint64_t a, b, c, d, diff, diff_best;

	uint64_t a, b, c, d, diff, diff_best;
@@ -762,8 +762,7 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, 
	/* Otherwise a < c && b >= d, do nothing */

	/* Otherwise a < c && b >= d, do nothing */

}

}





static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,

static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)

				     int reg)

{

{

	int refclk = LC_FREQ;

	int refclk = LC_FREQ;

	int n, p, r;

	int n, p, r;
@@ -929,10 +928,10 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, 
		link_clock = 270000;

		link_clock = 270000;

		break;

		break;

	case PORT_CLK_SEL_WRPLL1:

	case PORT_CLK_SEL_WRPLL1:

		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);

		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);

		break;

		break;

	case PORT_CLK_SEL_WRPLL2:

	case PORT_CLK_SEL_WRPLL2:

		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);

		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);

		break;

		break;

	case PORT_CLK_SEL_SPLL:

	case PORT_CLK_SEL_SPLL:

		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;

		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
@@ -1011,12 +1010,12 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, 
{

{

	uint64_t freq2k;

	uint64_t freq2k;

	unsigned p, n2, r2;

	unsigned p, n2, r2;

	struct wrpll_rnp best = { 0, 0, 0 };

	struct hsw_wrpll_rnp best = { 0, 0, 0 };

	unsigned budget;

	unsigned budget;





	freq2k = clock / 100;

	freq2k = clock / 100;





	budget = wrpll_get_budget_for_freq(clock);

	budget = hsw_wrpll_get_budget_for_freq(clock);





	/* Special case handling for 540 pixel clock: bypass WR PLL entirely

	/* Special case handling for 540 pixel clock: bypass WR PLL entirely

	 * and directly pass the LC PLL to it. */

	 * and directly pass the LC PLL to it. */
@@ -1060,7 +1059,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, 
		     n2++) {

		     n2++) {





			for (p = P_MIN; p <= P_MAX; p += P_INC)

			for (p = P_MIN; p <= P_MAX; p += P_INC)

				wrpll_update_rnp(freq2k, budget,

				hsw_wrpll_update_rnp(freq2k, budget,

						     r2, n2, p, &best);

						     r2, n2, p, &best);

		}

		}

	}

	}