Loading asoc/bengal-port-config.h +1 −1 Original line number Diff line number Diff line Loading @@ -37,7 +37,7 @@ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { }; static struct swr_mstr_port_map sm_port_map[] = { {TX_MACRO, SWR_UC0, tx_frame_params_default}, {VA_MACRO, SWR_UC0, tx_frame_params_default}, {RX_MACRO, SWR_UC0, rx_frame_params_default}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, }; Loading asoc/codecs/bolero/bolero-cdc-registers.h +1 −0 Original line number Diff line number Diff line Loading @@ -696,6 +696,7 @@ #define BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (VA_START_OFFSET + 0x0000) #define BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL \ (VA_START_OFFSET + 0x0004) #define BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL (VA_START_OFFSET + 0x0008) #define BOLERO_CDC_VA_TOP_CSR_TOP_CFG0 (VA_START_OFFSET + 0x0080) #define BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL (VA_START_OFFSET + 0x0084) #define BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL (VA_START_OFFSET + 0x0088) Loading asoc/codecs/bolero/bolero-cdc-regmap.c +1 −0 Original line number Diff line number Diff line Loading @@ -609,6 +609,7 @@ static const struct reg_default bolero_defaults[] = { /* VA macro */ { BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, { BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, { BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, { BOLERO_CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, { BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, { BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, Loading asoc/codecs/bolero/bolero-cdc-tables.c +2 −0 Original line number Diff line number Diff line Loading @@ -442,6 +442,7 @@ u8 bolero_rx_reg_access[BOLERO_CDC_RX_MACRO_MAX] = { u8 bolero_va_reg_access[BOLERO_CDC_VA_MACRO_MAX] = { [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG, Loading Loading @@ -567,6 +568,7 @@ u8 bolero_va_reg_access[BOLERO_CDC_VA_MACRO_MAX] = { u8 bolero_va_top_reg_access[BOLERO_CDC_VA_MACRO_TOP_MAX] = { [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG, Loading asoc/codecs/bolero/bolero-cdc-utils.c +6 −12 Original line number Diff line number Diff line Loading @@ -68,12 +68,9 @@ static int regmap_bus_read(void *context, const void *reg, size_t reg_size, reg_p = (u16 *)reg; macro_id = bolero_get_macro_id(priv->va_without_decimation, reg_p[0]); if (macro_id < 0 || !priv->macros_supported[macro_id]) { dev_err_ratelimited(dev, "%s: Unsupported macro %d or reg 0x%x is invalid\n", __func__, macro_id, reg_p[0]); return ret; } if (macro_id < 0 || !priv->macros_supported[macro_id]) return 0; mutex_lock(&priv->io_lock); for (i = 0; i < val_size; i++) { __reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id]; Loading Loading @@ -121,12 +118,9 @@ static int regmap_bus_gather_write(void *context, reg_p = (u16 *)reg; macro_id = bolero_get_macro_id(priv->va_without_decimation, reg_p[0]); if (macro_id < 0 || !priv->macros_supported[macro_id]) { dev_err_ratelimited(dev, "%s: Unsupported macro-id %d or reg 0x%x is invalid\n", __func__, macro_id, reg_p[0]); return ret; } if (macro_id < 0 || !priv->macros_supported[macro_id]) return 0; mutex_lock(&priv->io_lock); for (i = 0; i < val_size; i++) { __reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id]; Loading Loading
asoc/bengal-port-config.h +1 −1 Original line number Diff line number Diff line Loading @@ -37,7 +37,7 @@ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { }; static struct swr_mstr_port_map sm_port_map[] = { {TX_MACRO, SWR_UC0, tx_frame_params_default}, {VA_MACRO, SWR_UC0, tx_frame_params_default}, {RX_MACRO, SWR_UC0, rx_frame_params_default}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, }; Loading
asoc/codecs/bolero/bolero-cdc-registers.h +1 −0 Original line number Diff line number Diff line Loading @@ -696,6 +696,7 @@ #define BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (VA_START_OFFSET + 0x0000) #define BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL \ (VA_START_OFFSET + 0x0004) #define BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL (VA_START_OFFSET + 0x0008) #define BOLERO_CDC_VA_TOP_CSR_TOP_CFG0 (VA_START_OFFSET + 0x0080) #define BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL (VA_START_OFFSET + 0x0084) #define BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL (VA_START_OFFSET + 0x0088) Loading
asoc/codecs/bolero/bolero-cdc-regmap.c +1 −0 Original line number Diff line number Diff line Loading @@ -609,6 +609,7 @@ static const struct reg_default bolero_defaults[] = { /* VA macro */ { BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, { BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, { BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, { BOLERO_CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, { BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, { BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, Loading
asoc/codecs/bolero/bolero-cdc-tables.c +2 −0 Original line number Diff line number Diff line Loading @@ -442,6 +442,7 @@ u8 bolero_rx_reg_access[BOLERO_CDC_RX_MACRO_MAX] = { u8 bolero_va_reg_access[BOLERO_CDC_VA_MACRO_MAX] = { [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG, Loading Loading @@ -567,6 +568,7 @@ u8 bolero_va_reg_access[BOLERO_CDC_VA_MACRO_MAX] = { u8 bolero_va_top_reg_access[BOLERO_CDC_VA_MACRO_TOP_MAX] = { [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG, [BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG, Loading
asoc/codecs/bolero/bolero-cdc-utils.c +6 −12 Original line number Diff line number Diff line Loading @@ -68,12 +68,9 @@ static int regmap_bus_read(void *context, const void *reg, size_t reg_size, reg_p = (u16 *)reg; macro_id = bolero_get_macro_id(priv->va_without_decimation, reg_p[0]); if (macro_id < 0 || !priv->macros_supported[macro_id]) { dev_err_ratelimited(dev, "%s: Unsupported macro %d or reg 0x%x is invalid\n", __func__, macro_id, reg_p[0]); return ret; } if (macro_id < 0 || !priv->macros_supported[macro_id]) return 0; mutex_lock(&priv->io_lock); for (i = 0; i < val_size; i++) { __reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id]; Loading Loading @@ -121,12 +118,9 @@ static int regmap_bus_gather_write(void *context, reg_p = (u16 *)reg; macro_id = bolero_get_macro_id(priv->va_without_decimation, reg_p[0]); if (macro_id < 0 || !priv->macros_supported[macro_id]) { dev_err_ratelimited(dev, "%s: Unsupported macro-id %d or reg 0x%x is invalid\n", __func__, macro_id, reg_p[0]); return ret; } if (macro_id < 0 || !priv->macros_supported[macro_id]) return 0; mutex_lock(&priv->io_lock); for (i = 0; i < val_size; i++) { __reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id]; Loading