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Commit 62c7ae87 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: pci: Start unifying the SH7780 PCIC initialization. 



This starts moving out the common initialization bits from the various
fixup paths in to the shared init path.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent a6d377b6

arch/sh/drivers/pci/fixups-r7780rp.c

+1 −19
Original line number Diff line number Diff line
@@ -22,33 +22,15 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 
{

	return irq_tab[slot];

}



int pci_fixup_pcic(struct pci_channel *chan)

{

	pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);

	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);



	pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);

	pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);



	pci_write_reg(chan, 0x00011912, SH7780_PCISVID);

	pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);

	pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);

	pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);

	pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);



	pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);



#ifdef CONFIG_32BIT

	pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);

	pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);

#endif



	/* Set IOBR for windows containing area specified in pci.h */

	pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),

		      SH7780_PCIIOBR);

	pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),

		      SH7780_PCIIOBMR);



	return 0;

}

arch/sh/drivers/pci/fixups-sdk7780.c

+5 −27
Original line number Diff line number Diff line
@@ -35,40 +35,18 @@ int pci_fixup_pcic(struct pci_channel *chan) 
{

	/* Enable all interrupts, so we know what to fix */

	pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);

	pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);



	/* Set up standard PCI config registers */

	pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);

	pci_write_reg(chan, 0x0047, SH7780_PCICMD);

	pci_write_reg(chan, 0x00, SH7780_PCIPIF);

	pci_write_reg(chan, 0x1912, SH7780_PCISVID);

	pci_write_reg(chan, 0x0001, SH7780_PCISID);



	pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0);	/* PCI */

	pci_write_reg(chan, 0x08000000, SH7780_PCILAR0);	/* SHwy */

	pci_write_reg(chan, 0x07F00001, SH7780_PCILSR);	/* size 128M w/ MBAR */

	pci_write_reg(chan, 0x08000000, SH4_PCILAR0);	/* SHwy */

	pci_write_reg(chan, 0x07F00001, SH4_PCILSR0);	/* size 128M w/ MBAR */



	pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);

	pci_write_reg(chan, 0x00000000, SH4_PCILAR1);

	pci_write_reg(chan, 0x00000000, SH4_PCILSR1);



	pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);



	/*

	 * Set the MBR so PCI address is one-to-one with window,

	 * meaning all calls go straight through... use ifdef to

	 * catch erroneous assumption.

	 */

	pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0);	/* 16M */



	/* Set IOBR for window containing area specified in pci.h */

	pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),

		      SH7780_PCIIOBR);

	pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),

		      SH7780_PCIIOBMR);



	pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);

	pci_write_reg(chan, 0xA5000C01, SH4_PCICR);



	return 0;

}

arch/sh/drivers/pci/pci-sh7780.c

+31 −19
Original line number Diff line number Diff line 
/*

 * Low-Level PCI Support for the SH7780

 *

 *  Dustin McIntire (dustin@sensoria.com)

 *	Derived from arch/i386/kernel/pci-*.c which bore the message:

 *	(c) 1999--2000 Martin Mares <mj@ucw.cz>

 *

 *  Ported to the new API by Paul Mundt <lethal@linux-sh.org>

 *  With cleanup by Paul van Gool <pvangool@mimotech.com>

 *

 *  May be copied or modified under the terms of the GNU General Public

 *  License.  See linux/COPYING for more information.

 *  Copyright (C) 2005 - 2009  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#undef DEBUG



#include <linux/types.h>

#include <linux/kernel.h>

#include <linux/init.h>
@@ -117,13 +110,8 @@ int __init pcibios_init_platform(void) 


	pci_cache_line_size = pci_read_reg(chan, SH7780_PCICLS) / 4;



	/* set the command/status bits to:

	 * Wait Cycle Control + Parity Enable + Bus Master +

	 * Mem space enable

	 */

	pci_write_reg(chan, 0x00000046, SH7780_PCICMD);



	/* Set IO and Mem windows to local address

	/*

	 * Set IO and Mem windows to local address

	 * Make PCI and local address the same for easy 1 to 1 mapping

	 */

	pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
@@ -131,9 +119,33 @@ int __init pcibios_init_platform(void) 
	pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);

	pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);



	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);



	/* Set up standard PCI config registers */

	__raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);

	__raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);

	__raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);

	__raw_writew(0x0001, chan->reg_base + SH7780_PCISID);



	__raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);



	/* Apply any last-minute PCIC fixups */

	pci_fixup_pcic(chan);



	pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);



#ifdef CONFIG_32BIT

	pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);

	pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);

#endif



	/* Set IOBR for windows containing area specified in pci.h */

	pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),

		      SH7780_PCIIOBR);

	pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),

		      SH7780_PCIIOBMR);



	/* SH7780 init done, set central function init complete */

	/* use round robin mode to stop a device starving/overruning */

	word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;

arch/sh/drivers/pci/pci-sh7780.h

+0 −5
Original line number Diff line number Diff line
@@ -65,11 +65,6 @@ 
#define SH7780_PCIPMCSR_BSE	0x046

#define SH7780_PCICDD		0x047



#define SH7780_PCICR		0x100		/* PCI Control Register */

#define SH7780_PCILSR		0x104		/* PCI Local Space Register0 */

#define SH7780_PCILSR1		0x108		/* PCI Local Space Register1 */

#define SH7780_PCILAR0		0x10C		/* PCI Local Address Register1 */

#define SH7780_PCILAR1		0x110		/* PCI Local Address Register1 */

#define SH7780_PCIIR		0x114		/* PCI Interrupt Register */

#define SH7780_PCIIMR		0x118		/* PCI Interrupt Mask Register */

#define SH7780_PCIAIR		0x11C		/* Error Address Register */