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Commit 628665d2 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Move memstore allocation to adreno"

parents 2a575e97 71f4dcac

drivers/gpu/msm/adreno.c

+9 −0
Original line number Diff line number Diff line
@@ -1427,6 +1427,12 @@ static int adreno_probe(struct platform_device *pdev) 
	if (ADRENO_FEATURE(adreno_dev, ADRENO_IOCOHERENT))

		device->mmu.features |= KGSL_MMU_IO_COHERENT;



	/* Allocate the memstore for storing timestamps and other useful info */

	status = kgsl_allocate_global(device, &device->memstore,

		KGSL_MEMSTORE_SIZE, 0, KGSL_MEMDESC_CONTIG, "memstore");

	if (status)

		goto out;



	status = adreno_ringbuffer_probe(adreno_dev);

	if (status)

		goto out;
@@ -1478,6 +1484,7 @@ static int adreno_probe(struct platform_device *pdev) 
out:

	if (status) {

		adreno_ringbuffer_close(adreno_dev);

		kgsl_free_global(device, &device->memstore);

		kgsl_device_platform_remove(device);

		device->pdev = NULL;

	}
@@ -1558,6 +1565,8 @@ static int adreno_remove(struct platform_device *pdev) 
	if (efuse_base != NULL)

		iounmap(efuse_base);



	kgsl_free_global(device, &device->memstore);



	kgsl_device_platform_remove(device);



	gmu_core_remove(device);

drivers/gpu/msm/adreno.h

+0 −1
Original line number Diff line number Diff line
@@ -606,7 +606,6 @@ enum adreno_regs { 
	ADRENO_REG_CP_ME_RAM_DATA,

	ADRENO_REG_CP_PFP_UCODE_DATA,

	ADRENO_REG_CP_PFP_UCODE_ADDR,

	ADRENO_REG_CP_WFI_PEND_CTR,

	ADRENO_REG_CP_RB_BASE,

	ADRENO_REG_CP_RB_BASE_HI,

	ADRENO_REG_CP_RB_RPTR_ADDR_LO,

drivers/gpu/msm/adreno_a3xx.c

+0 −1
Original line number Diff line number Diff line
@@ -1232,7 +1232,6 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_DATA, A3XX_CP_ME_RAM_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_DATA, A3XX_CP_PFP_UCODE_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_ADDR, A3XX_CP_PFP_UCODE_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_WFI_PEND_CTR, A3XX_CP_WFI_PEND_CTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A3XX_CP_RB_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, ADRENO_REG_SKIP),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A3XX_CP_RB_RPTR),

drivers/gpu/msm/adreno_a5xx.c

+0 −1
Original line number Diff line number Diff line
@@ -2498,7 +2498,6 @@ static unsigned int a5xx_int_bits[ADRENO_INT_BITS_MAX] = { 


/* Register offset defines for A5XX, in order of enum adreno_regs */

static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {

	ADRENO_REG_DEFINE(ADRENO_REG_CP_WFI_PEND_CTR, A5XX_CP_WFI_PEND_CTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A5XX_CP_RB_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, A5XX_CP_RB_BASE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR_ADDR_LO,

drivers/gpu/msm/adreno_a6xx.h

+0 −2
Original line number Diff line number Diff line
@@ -151,8 +151,6 @@ struct cpu_gpu_lock { 
#define A6XX_CP_CTXRECORD_MAGIC_REF     0xAE399D6EUL

/* Size of each CP preemption record */

#define A6XX_CP_CTXRECORD_SIZE_IN_BYTES     (2112 * 1024)

/* Size of the preemption counter block (in bytes) */

#define A6XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE   (16 * 4)

/* Size of the user context record block (in bytes) */

#define A6XX_CP_CTXRECORD_USER_RESTORE_SIZE (192 * 1024)

/* Size of the performance counter save/restore block (in bytes) */