Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 62810e5a authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too 



Only two things needed adjustment:
- pipe select for PCH_CPT
- There's no dithering bit on ilk+ in the lvds ctl reg

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fc683091

drivers/gpu/drm/i915/intel_display.c

+0 −40
Original line number Diff line number Diff line
@@ -5322,7 +5322,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	bool ok, has_reduced_clock = false;

	bool is_lvds = false, is_dp = false, is_cpu_edp = false;

	struct intel_encoder *encoder;

	u32 temp;

	int ret;

	bool dither, fdi_config_ok;
@@ -5386,45 +5385,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	} else

		intel_put_pch_pll(intel_crtc);



	/* The LVDS pin pair needs to be on before the DPLLs are enabled.

	 * This is an exception to the general rule that mode_set doesn't turn

	 * things on.

	 */

	if (is_lvds) {

		temp = I915_READ(PCH_LVDS);

		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;

		if (HAS_PCH_CPT(dev)) {

			temp &= ~PORT_TRANS_SEL_MASK;

			temp |= PORT_TRANS_SEL_CPT(pipe);

		} else {

			if (pipe == 1)

				temp |= LVDS_PIPEB_SELECT;

			else

				temp &= ~LVDS_PIPEB_SELECT;

		}



		/* set the corresponsding LVDS_BORDER bit */

		temp |= dev_priv->lvds_border_bits;

		/* Set the B0-B3 data pairs corresponding to whether we're going to

		 * set the DPLLs for dual-channel mode or not.

		 */

		if (clock.p2 == 7)

			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;

		else

			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);



		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)

		 * appropriately here, but we need to look more thoroughly into how

		 * panels behave in the two modes.

		 */

		temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);

		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)

			temp |= LVDS_HSYNC_POLARITY;

		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)

			temp |= LVDS_VSYNC_POLARITY;

		I915_WRITE(PCH_LVDS, temp);

	}



	if (is_dp && !is_cpu_edp) {

		intel_dp_set_m_n(crtc, mode, adjusted_mode);

	} else {

drivers/gpu/drm/i915/intel_lvds.c

+15 −9
Original line number Diff line number Diff line
@@ -104,17 +104,20 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) 
	int pipe = intel_crtc->pipe;

	u32 temp;



	/* pch split platforms are not yet converted. */

	if (HAS_PCH_SPLIT(dev))

		return;



	temp = I915_READ(lvds_encoder->reg);

	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;



	if (HAS_PCH_CPT(dev)) {

		temp &= ~PORT_TRANS_SEL_MASK;

		temp |= PORT_TRANS_SEL_CPT(pipe);

	} else {

		if (pipe == 1) {

			temp |= LVDS_PIPEB_SELECT;

		} else {

			temp &= ~LVDS_PIPEB_SELECT;

		}

	}



	/* set the corresponsding LVDS_BORDER bit */

	temp |= dev_priv->lvds_border_bits;

	/* Set the B0-B3 data pairs corresponding to whether we're going to
@@ -129,8 +132,11 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) 
	 * appropriately here, but we need to look more thoroughly into how

	 * panels behave in the two modes.

	 */

	/* set the dithering flag on LVDS as needed */

	if (INTEL_INFO(dev)->gen >= 4) {



	/* Set the dithering flag on LVDS as needed, note that there is no

	 * special lvds dither control bit on pch-split platforms, dithering is

	 * only controlled through the PIPECONF reg. */

	if (INTEL_INFO(dev)->gen == 4) {

		if (dev_priv->lvds_dither)

			temp |= LVDS_ENABLE_DITHER;

		else