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Commit 6249ecbb authored by James Hogan's avatar James Hogan Committed by Ralf Baechle
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MIPS: Malta: Make GIC FDC IRQ workaround Malta specific 



Wider testing reveals that the Fast Debug Channel (FDC) interrupt is
routed through the GIC just fine on Pistachio SoC, even though it
contains interAptiv cores. Clearly the FDC interrupt routing problems
previously observed on interAptiv and proAptiv cores are specific to the
Malta FPGA bitstreams.

Move the workaround for interAptiv and proAptiv out of
gic_get_c0_fdc_int() in the GIC irqchip driver into Malta's
get_c0_fdc_int() platform callback, to allow the Pistachio SoC to use
the FDC interrupt.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Reviewed-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/9748/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent cccf34e9

arch/mips/mti-malta/malta-time.c

+13 −7
Original line number Original line Diff line number Diff line
@@ -119,18 +119,24 @@ void read_persistent_clock(struct timespec *ts) 




int get_c0_fdc_int(void)

int get_c0_fdc_int(void)

{

{

	int mips_cpu_fdc_irq;

	/*

	 * Some cores claim the FDC is routable through the GIC, but it doesn't

	 * actually seem to be connected for those Malta bitstreams.

	 */

	switch (current_cpu_type()) {

	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

		return -1;

	};





	if (cpu_has_veic)

	if (cpu_has_veic)

		mips_cpu_fdc_irq = -1;

		return -1;

	else if (gic_present)

	else if (gic_present)

		mips_cpu_fdc_irq = gic_get_c0_fdc_int();

		return gic_get_c0_fdc_int();

	else if (cp0_fdc_irq >= 0)

	else if (cp0_fdc_irq >= 0)

		mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;

		return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;

	else

	else

		mips_cpu_fdc_irq = -1;

		return -1;



	return mips_cpu_fdc_irq;

}

}





int get_c0_perfcount_int(void)

int get_c0_perfcount_int(void)

drivers/irqchip/irq-mips-gic.c

+0 −10
Original line number Original line Diff line number Diff line
@@ -257,16 +257,6 @@ int gic_get_c0_fdc_int(void) 
		return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;

		return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;

	}

	}





	/*

	 * Some cores claim the FDC is routable but it doesn't actually seem to

	 * be connected.

	 */

	switch (current_cpu_type()) {

	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

		return -1;

	}



	return irq_create_mapping(gic_irq_domain,

	return irq_create_mapping(gic_irq_domain,

				  GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));

				  GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));

}

}