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Commit 61a8dec5 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Mark Brown
Browse files

spi: sh-msiof: Limit minimum divider on R-Car Gen3 



On R-Car Gen3 SoCs (excluding R-Car H3 ES1.x, which cannot be used for
SPI due to a hardware erratum), BRPS x BRDV = 1/1 is an invalid divider
setting.
Implement this limitation using an SoC/family-specific minimum divider.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 3d108f1e

drivers/spi/spi-sh-msiof.c

+23 −9
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ struct sh_msiof_chipdata { 
	u16 tx_fifo_size;

	u16 rx_fifo_size;

	u16 master_flags;

	u16 min_div;

};



struct sh_msiof_spi_priv {
@@ -49,6 +50,7 @@ struct sh_msiof_spi_priv { 
	struct completion done;

	unsigned int tx_fifo_size;

	unsigned int rx_fifo_size;

	unsigned int min_div;

	void *tx_dma_page;

	void *rx_dma_page;

	dma_addr_t tx_dma_addr;
@@ -261,6 +263,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 
	if (!WARN_ON(!spi_hz || !parent_rate))

		div = DIV_ROUND_UP(parent_rate, spi_hz);



	div = max_t(unsigned long, div, p->min_div);



	for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {

		brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);

		/* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
@@ -998,24 +1002,33 @@ static const struct sh_msiof_chipdata sh_data = { 
	.tx_fifo_size = 64,

	.rx_fifo_size = 64,

	.master_flags = 0,

	.min_div = 1,

};



static const struct sh_msiof_chipdata rcar_gen2_data = {

	.tx_fifo_size = 64,

	.rx_fifo_size = 64,

	.master_flags = SPI_MASTER_MUST_TX,

	.min_div = 1,

};



static const struct sh_msiof_chipdata r8a779x_data = {

static const struct sh_msiof_chipdata rcar_gen3_data = {

	.tx_fifo_size = 64,

	.rx_fifo_size = 64,

	.master_flags = SPI_MASTER_MUST_TX,

	.min_div = 2,

};



static const struct of_device_id sh_msiof_match[] = {

	{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },

	{ .compatible = "renesas,msiof-r8a7790",   .data = &r8a779x_data },

	{ .compatible = "renesas,msiof-r8a7791",   .data = &r8a779x_data },

	{ .compatible = "renesas,msiof-r8a7792",   .data = &r8a779x_data },

	{ .compatible = "renesas,msiof-r8a7793",   .data = &r8a779x_data },

	{ .compatible = "renesas,msiof-r8a7794",   .data = &r8a779x_data },

	{ .compatible = "renesas,rcar-gen2-msiof", .data = &r8a779x_data },

	{ .compatible = "renesas,msiof-r8a7796",   .data = &r8a779x_data },

	{ .compatible = "renesas,rcar-gen3-msiof", .data = &r8a779x_data },

	{ .compatible = "renesas,msiof-r8a7790",   .data = &rcar_gen2_data },

	{ .compatible = "renesas,msiof-r8a7791",   .data = &rcar_gen2_data },

	{ .compatible = "renesas,msiof-r8a7792",   .data = &rcar_gen2_data },

	{ .compatible = "renesas,msiof-r8a7793",   .data = &rcar_gen2_data },

	{ .compatible = "renesas,msiof-r8a7794",   .data = &rcar_gen2_data },

	{ .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },

	{ .compatible = "renesas,msiof-r8a7796",   .data = &rcar_gen3_data },

	{ .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },

	{ .compatible = "renesas,sh-msiof",        .data = &sh_data }, /* Deprecated */

	{},

};
@@ -1230,6 +1243,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) 
	platform_set_drvdata(pdev, p);

	p->master = master;

	p->info = info;

	p->min_div = chipdata->min_div;



	init_completion(&p->done);