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Commit 6157bd7a authored by Flora Cui's avatar Flora Cui Committed by Alex Deucher
Browse files

drm/amdgpu: fix rb bitmap & cu bitmap calculation 



Fix some copy paste typos.

Signed-off-by: default avatarFlora Cui <Flora.Cui@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 22073fe7

drivers/gpu/drm/amd/amdgpu/cikd.h

+0 −3
Original line number Diff line number Diff line
@@ -46,9 +46,6 @@ 
#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001

#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003



#define CIK_RB_BITMAP_WIDTH_PER_SH     2

#define HAWAII_RB_BITMAP_WIDTH_PER_SH  4



#define AMDGPU_NUM_OF_VMIDS	8



#define		PIPEID(x)					((x) << 0)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+7 −8
Original line number Diff line number Diff line
@@ -1637,18 +1637,16 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 
	int i, j;

	u32 data;

	u32 active_rbs = 0;

	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

					adev->gfx.config.max_sh_per_se;



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

			gfx_v7_0_select_se_sh(adev, i, j);

			data = gfx_v7_0_get_rb_active_bitmap(adev);

			if (adev->asic_type == CHIP_HAWAII)

			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

						       HAWAII_RB_BITMAP_WIDTH_PER_SH);

			else

				active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

						       CIK_RB_BITMAP_WIDTH_PER_SH);

					       rb_bitmap_width_per_sh);

		}

	}

	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
@@ -3820,8 +3818,7 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 
	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;

	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;



	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /

				       adev->gfx.config.max_sh_per_se);

	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);



	return (~data) & mask;

}
@@ -5232,6 +5229,8 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, 
	if (!adev || !cu_info)

		return -EINVAL;



	memset(cu_info, 0, sizeof(*cu_info));



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+6 −3
Original line number Diff line number Diff line
@@ -2615,6 +2615,8 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) 
	int i, j;

	u32 data;

	u32 active_rbs = 0;

	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

					adev->gfx.config.max_sh_per_se;



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
@@ -2622,7 +2624,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) 
			gfx_v8_0_select_se_sh(adev, i, j);

			data = gfx_v8_0_get_rb_active_bitmap(adev);

			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

					       RB_BITMAP_WIDTH_PER_SH);

					       rb_bitmap_width_per_sh);

		}

	}

	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
@@ -5126,8 +5128,7 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev) 
	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;

	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;



	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /

				       adev->gfx.config.max_sh_per_se);

	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);



	return (~data) & mask;

}
@@ -5141,6 +5142,8 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, 
	if (!adev || !cu_info)

		return -EINVAL;



	memset(cu_info, 0, sizeof(*cu_info));



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

drivers/gpu/drm/amd/amdgpu/vid.h

+0 −2
Original line number Diff line number Diff line
@@ -71,8 +71,6 @@ 
#define		VMID(x)						((x) << 4)

#define		QUEUEID(x)					((x) << 8)



#define RB_BITMAP_WIDTH_PER_SH     2



#define MC_SEQ_MISC0__MT__MASK	0xf0000000

#define MC_SEQ_MISC0__MT__GDDR1  0x10000000

#define MC_SEQ_MISC0__MT__DDR2   0x20000000