Loading asoc/codecs/audio-ext-clk-up.c +12 −0 Original line number Diff line number Diff line Loading @@ -70,6 +70,8 @@ static int audio_ext_clk_prepare(struct clk_hw *hw) if ((clk_priv->clk_src >= AUDIO_EXT_CLK_LPASS) && (clk_priv->clk_src < AUDIO_EXT_CLK_LPASS_MAX)) { clk_priv->clk_cfg.enable = 1; trace_printk("%s: vote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk_priv->clk_cfg); if (ret < 0) { pr_err_ratelimited("%s afe_set_digital_codec_core_clock failed\n", Loading Loading @@ -112,6 +114,8 @@ static void audio_ext_clk_unprepare(struct clk_hw *hw) if ((clk_priv->clk_src >= AUDIO_EXT_CLK_LPASS) && (clk_priv->clk_src < AUDIO_EXT_CLK_LPASS_MAX)) { clk_priv->clk_cfg.enable = 0; trace_printk("%s: unvote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk_priv->clk_cfg); if (ret < 0) pr_err_ratelimited("%s: afe_set_lpass_clk_cfg failed, ret = %d\n", Loading Loading @@ -146,6 +150,8 @@ static int lpass_hw_vote_prepare(struct clk_hw *hw) int ret; if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE) { trace_printk("%s: vote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_vote_lpass_core_hw(AFE_LPASS_CORE_HW_MACRO_BLOCK, "LPASS_HW_MACRO", &clk_priv->lpass_core_hwvote_client_handle); Loading @@ -157,6 +163,8 @@ static int lpass_hw_vote_prepare(struct clk_hw *hw) } if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE) { trace_printk("%s: vote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_vote_lpass_core_hw(AFE_LPASS_CORE_HW_DCODEC_BLOCK, "LPASS_HW_DCODEC", &clk_priv->lpass_audio_hwvote_client_handle); Loading @@ -176,6 +184,8 @@ static void lpass_hw_vote_unprepare(struct clk_hw *hw) int ret = 0; if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE) { trace_printk("%s: unvote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_unvote_lpass_core_hw( AFE_LPASS_CORE_HW_MACRO_BLOCK, clk_priv->lpass_core_hwvote_client_handle); Loading @@ -186,6 +196,8 @@ static void lpass_hw_vote_unprepare(struct clk_hw *hw) } if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE) { trace_printk("%s: unvote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_unvote_lpass_core_hw( AFE_LPASS_CORE_HW_DCODEC_BLOCK, clk_priv->lpass_audio_hwvote_client_handle); Loading asoc/codecs/bolero/bolero-cdc.c +11 −0 Original line number Diff line number Diff line Loading @@ -828,6 +828,7 @@ static int bolero_ssr_enable(struct device *dev, void *data) priv->component, BOLERO_MACRO_EVT_CLK_RESET, 0x0); } trace_printk("%s: clk count reset\n", __func__); regcache_cache_only(priv->regmap, false); mutex_lock(&priv->clk_lock); priv->dev_up = true; Loading @@ -838,6 +839,7 @@ static int bolero_ssr_enable(struct device *dev, void *data) /* Add a 100usec sleep to ensure last register write is done */ usleep_range(100,110); bolero_clk_rsc_enable_all_clocks(priv->clk_dev, false); trace_printk("%s: regcache_sync done\n", __func__); /* call ssr event for supported macros */ for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) { if (!priv->macro_params[macro_idx].event_handler) Loading @@ -846,6 +848,7 @@ static int bolero_ssr_enable(struct device *dev, void *data) priv->component, BOLERO_MACRO_EVT_SSR_UP, 0x0); } trace_printk("%s: SSR up events processed by all macros\n", __func__); bolero_cdc_notifier_call(priv, BOLERO_WCD_EVT_SSR_UP); return 0; } Loading Loading @@ -1374,6 +1377,8 @@ int bolero_runtime_resume(struct device *dev) } } priv->core_hw_vote_count++; trace_printk("%s: hw vote count %d\n", __func__, priv->core_hw_vote_count); audio_vote: if (priv->lpass_audio_hw_vote == NULL) { Loading @@ -1390,6 +1395,8 @@ int bolero_runtime_resume(struct device *dev) } } priv->core_audio_vote_count++; trace_printk("%s: audio vote count %d\n", __func__, priv->core_audio_vote_count); done: mutex_unlock(&priv->vote_lock); Loading @@ -1412,6 +1419,8 @@ int bolero_runtime_suspend(struct device *dev) dev_dbg(dev, "%s: Invalid lpass core hw node\n", __func__); } trace_printk("%s: hw vote count %d\n", __func__, priv->core_hw_vote_count); if (priv->lpass_audio_hw_vote != NULL) { if (--priv->core_audio_vote_count == 0) Loading @@ -1422,6 +1431,8 @@ int bolero_runtime_suspend(struct device *dev) dev_dbg(dev, "%s: Invalid lpass audio hw node\n", __func__); } trace_printk("%s: audio vote count %d\n", __func__, priv->core_audio_vote_count); mutex_unlock(&priv->vote_lock); return 0; Loading asoc/codecs/bolero/bolero-clk-rsc.c +13 −0 Original line number Diff line number Diff line Loading @@ -129,6 +129,8 @@ int bolero_rsc_clk_reset(struct device *dev, int clk_id) } dev_dbg(priv->dev, "%s: clock reset after ssr, count %d\n", __func__, count); trace_printk("%s: clock reset after ssr, count %d\n", __func__, count); while (count--) { clk_prepare_enable(priv->clk[clk_id]); clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]); Loading Loading @@ -238,6 +240,7 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, char __iomem *clk_muxsel = NULL; int ret = 0; int default_clk_id = priv->default_clk_id[clk_id]; u32 muxsel = 0; clk_muxsel = bolero_clk_rsc_get_clk_muxsel(priv, clk_id); if (!clk_muxsel) { Loading Loading @@ -269,6 +272,9 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, } } iowrite32(0x1, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after enable: %d\n", __func__, muxsel); bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false); } Loading @@ -288,6 +294,9 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, if (!ret) iowrite32(0x0, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after disable: %d\n", __func__, muxsel); if (priv->clk[clk_id + NPL_CLK_OFFSET]) clk_disable_unprepare( priv->clk[clk_id + NPL_CLK_OFFSET]); Loading Loading @@ -504,6 +513,7 @@ int bolero_clk_rsc_request_clock(struct device *dev, if (!priv->dev_up && enable) { dev_err_ratelimited(priv->dev, "%s: SSR is in progress..\n", __func__); trace_printk("%s: SSR is in progress..\n", __func__); ret = -EINVAL; goto err; } Loading Loading @@ -533,6 +543,9 @@ int bolero_clk_rsc_request_clock(struct device *dev, dev_dbg(priv->dev, "%s: clk_cnt: %d for requested clk: %d, enable: %d\n", __func__, priv->clk_cnt[clk_id_req], clk_id_req, enable); trace_printk("%s: clk_cnt: %d for requested clk: %d, enable: %d\n", __func__, priv->clk_cnt[clk_id_req], clk_id_req, enable); mutex_unlock(&priv->rsc_clk_lock); Loading asoc/codecs/bolero/rx-macro.c +8 −0 Original line number Diff line number Diff line Loading @@ -1284,6 +1284,8 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, } } exit: trace_printk("%s: mclk_enable = %u, dapm = %d clk_users= %d\n", __func__, mclk_enable, dapm, rx_priv->rx_mclk_users); mutex_unlock(&rx_priv->mclk_lock); return ret; } Loading Loading @@ -1369,6 +1371,7 @@ static int rx_macro_event_handler(struct snd_soc_component *component, rx_macro_wcd_clsh_imped_config(component, data, false); break; case BOLERO_MACRO_EVT_SSR_DOWN: trace_printk("%s, enter SSR down\n", __func__); rx_priv->dev_up = false; if (rx_priv->swr_ctrl_data) { swrm_wcd_notify( Loading @@ -1389,6 +1392,7 @@ static int rx_macro_event_handler(struct snd_soc_component *component, } break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); rx_priv->dev_up = true; /* reset swr after ssr/pdr */ rx_priv->reset_swr = true; Loading Loading @@ -3636,6 +3640,8 @@ static int rx_swrm_clock(void *handle, bool enable) mutex_lock(&rx_priv->swr_clk_lock); trace_printk("%s: swrm clock %s\n", __func__, (enable ? "enable" : "disable")); dev_dbg(rx_priv->dev, "%s: swrm clock %s\n", __func__, (enable ? "enable" : "disable")); if (enable) { Loading Loading @@ -3702,6 +3708,8 @@ static int rx_swrm_clock(void *handle, bool enable) } } } trace_printk("%s: swrm clock users %d\n", __func__, rx_priv->swr_clk_users); dev_dbg(rx_priv->dev, "%s: swrm clock users %d\n", __func__, rx_priv->swr_clk_users); exit: Loading asoc/codecs/bolero/tx-macro.c +42 −15 Original line number Diff line number Diff line Loading @@ -373,6 +373,7 @@ static int tx_macro_event_handler(struct snd_soc_component *component, switch (event) { case BOLERO_MACRO_EVT_SSR_DOWN: trace_printk("%s, enter SSR down\n", __func__); if (tx_priv->swr_ctrl_data) { swrm_wcd_notify( tx_priv->swr_ctrl_data[0].tx_swr_pdev, Loading @@ -392,6 +393,7 @@ static int tx_macro_event_handler(struct snd_soc_component *component, } break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); /* reset swr after ssr/pdr */ tx_priv->reset_swr = true; if (tx_priv->swr_ctrl_data) Loading Loading @@ -883,13 +885,14 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMU: snd_soc_component_update_bits(component, tx_vol_ctl_reg, 0x20, 0x20); if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) { snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00); /* * Minimum 1 clk cycle delay is required as per HW spec */ usleep_range(1000, 1010); } hpf_cut_off_freq = ( snd_soc_component_read32(component, dec_cfg_reg) & TX_HPF_CUT_OFF_FREQ_MASK) >> 5; Loading Loading @@ -917,15 +920,17 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, &tx_priv->tx_hpf_work[decimator].dwork, msecs_to_jiffies(hpf_delay)); snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x03); hpf_gate_reg, 0x03, 0x02); if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x00); /* * Minimum 1 clk cycle delay is required as per HW spec */ usleep_range(1000, 1010); snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00); snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x01); hpf_gate_reg, 0x03, 0x01); /* * 6ms delay is required as per HW spec */ Loading Loading @@ -957,9 +962,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, component, dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK, hpf_cut_off_freq << 5); if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX) snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02); 0x03, 0x02); else snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x03); /* * Minimum 1 clk cycle delay is required * as per HW spec Loading @@ -967,7 +978,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, usleep_range(1000, 1010); snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00); 0x03, 0x01); } } cancel_delayed_work_sync( Loading Loading @@ -2356,6 +2367,9 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, { int ret = 0, clk_tx_ret = 0; trace_printk("%s: clock type %s, enable: %s tx_mclk_users: %d\n", __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"), (enable ? "enable" : "disable"), tx_priv->tx_mclk_users); dev_dbg(tx_priv->dev, "%s: clock type %s, enable: %s tx_mclk_users: %d\n", __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"), Loading @@ -2363,6 +2377,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, if (enable) { if (tx_priv->swr_clk_users == 0) { trace_printk("%s: tx swr clk users 0\n", __func__); ret = msm_cdc_pinctrl_select_active_state( tx_priv->tx_swr_gpio_p); if (ret < 0) { Loading @@ -2378,6 +2393,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, TX_CORE_CLK, true); if (clk_type == TX_MCLK) { trace_printk("%s: requesting TX_MCLK\n", __func__); ret = tx_macro_mclk_enable(tx_priv, 1); if (ret < 0) { if (tx_priv->swr_clk_users == 0) Loading @@ -2390,6 +2406,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, } } if (clk_type == VA_MCLK) { trace_printk("%s: requesting VA_MCLK\n", __func__); ret = bolero_clk_rsc_request_clock(tx_priv->dev, TX_CORE_CLK, VA_CORE_CLK, Loading Loading @@ -2421,6 +2438,8 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, if (tx_priv->swr_clk_users == 0) { dev_dbg(tx_priv->dev, "%s: reset_swr: %d\n", __func__, tx_priv->reset_swr); trace_printk("%s: reset_swr: %d\n", __func__, tx_priv->reset_swr); if (tx_priv->reset_swr) regmap_update_bits(regmap, BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, Loading Loading @@ -2514,6 +2533,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, TX_CORE_CLK, false); exit: trace_printk("%s: exit\n", __func__); return ret; } Loading Loading @@ -2590,6 +2610,10 @@ static int tx_macro_swrm_clock(void *handle, bool enable) } mutex_lock(&tx_priv->swr_clk_lock); trace_printk("%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n", __func__, (enable ? "enable" : "disable"), tx_priv->tx_swr_clk_cnt, tx_priv->va_swr_clk_cnt); dev_dbg(tx_priv->dev, "%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n", __func__, (enable ? "enable" : "disable"), Loading Loading @@ -2652,6 +2676,9 @@ static int tx_macro_swrm_clock(void *handle, bool enable) } } trace_printk("%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n", __func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status, tx_priv->va_clk_status); dev_dbg(tx_priv->dev, "%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n", __func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status, Loading Loading
asoc/codecs/audio-ext-clk-up.c +12 −0 Original line number Diff line number Diff line Loading @@ -70,6 +70,8 @@ static int audio_ext_clk_prepare(struct clk_hw *hw) if ((clk_priv->clk_src >= AUDIO_EXT_CLK_LPASS) && (clk_priv->clk_src < AUDIO_EXT_CLK_LPASS_MAX)) { clk_priv->clk_cfg.enable = 1; trace_printk("%s: vote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk_priv->clk_cfg); if (ret < 0) { pr_err_ratelimited("%s afe_set_digital_codec_core_clock failed\n", Loading Loading @@ -112,6 +114,8 @@ static void audio_ext_clk_unprepare(struct clk_hw *hw) if ((clk_priv->clk_src >= AUDIO_EXT_CLK_LPASS) && (clk_priv->clk_src < AUDIO_EXT_CLK_LPASS_MAX)) { clk_priv->clk_cfg.enable = 0; trace_printk("%s: unvote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk_priv->clk_cfg); if (ret < 0) pr_err_ratelimited("%s: afe_set_lpass_clk_cfg failed, ret = %d\n", Loading Loading @@ -146,6 +150,8 @@ static int lpass_hw_vote_prepare(struct clk_hw *hw) int ret; if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE) { trace_printk("%s: vote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_vote_lpass_core_hw(AFE_LPASS_CORE_HW_MACRO_BLOCK, "LPASS_HW_MACRO", &clk_priv->lpass_core_hwvote_client_handle); Loading @@ -157,6 +163,8 @@ static int lpass_hw_vote_prepare(struct clk_hw *hw) } if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE) { trace_printk("%s: vote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_vote_lpass_core_hw(AFE_LPASS_CORE_HW_DCODEC_BLOCK, "LPASS_HW_DCODEC", &clk_priv->lpass_audio_hwvote_client_handle); Loading @@ -176,6 +184,8 @@ static void lpass_hw_vote_unprepare(struct clk_hw *hw) int ret = 0; if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE) { trace_printk("%s: unvote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_unvote_lpass_core_hw( AFE_LPASS_CORE_HW_MACRO_BLOCK, clk_priv->lpass_core_hwvote_client_handle); Loading @@ -186,6 +196,8 @@ static void lpass_hw_vote_unprepare(struct clk_hw *hw) } if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE) { trace_printk("%s: unvote for %d clock\n", __func__, clk_priv->clk_src); ret = afe_unvote_lpass_core_hw( AFE_LPASS_CORE_HW_DCODEC_BLOCK, clk_priv->lpass_audio_hwvote_client_handle); Loading
asoc/codecs/bolero/bolero-cdc.c +11 −0 Original line number Diff line number Diff line Loading @@ -828,6 +828,7 @@ static int bolero_ssr_enable(struct device *dev, void *data) priv->component, BOLERO_MACRO_EVT_CLK_RESET, 0x0); } trace_printk("%s: clk count reset\n", __func__); regcache_cache_only(priv->regmap, false); mutex_lock(&priv->clk_lock); priv->dev_up = true; Loading @@ -838,6 +839,7 @@ static int bolero_ssr_enable(struct device *dev, void *data) /* Add a 100usec sleep to ensure last register write is done */ usleep_range(100,110); bolero_clk_rsc_enable_all_clocks(priv->clk_dev, false); trace_printk("%s: regcache_sync done\n", __func__); /* call ssr event for supported macros */ for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) { if (!priv->macro_params[macro_idx].event_handler) Loading @@ -846,6 +848,7 @@ static int bolero_ssr_enable(struct device *dev, void *data) priv->component, BOLERO_MACRO_EVT_SSR_UP, 0x0); } trace_printk("%s: SSR up events processed by all macros\n", __func__); bolero_cdc_notifier_call(priv, BOLERO_WCD_EVT_SSR_UP); return 0; } Loading Loading @@ -1374,6 +1377,8 @@ int bolero_runtime_resume(struct device *dev) } } priv->core_hw_vote_count++; trace_printk("%s: hw vote count %d\n", __func__, priv->core_hw_vote_count); audio_vote: if (priv->lpass_audio_hw_vote == NULL) { Loading @@ -1390,6 +1395,8 @@ int bolero_runtime_resume(struct device *dev) } } priv->core_audio_vote_count++; trace_printk("%s: audio vote count %d\n", __func__, priv->core_audio_vote_count); done: mutex_unlock(&priv->vote_lock); Loading @@ -1412,6 +1419,8 @@ int bolero_runtime_suspend(struct device *dev) dev_dbg(dev, "%s: Invalid lpass core hw node\n", __func__); } trace_printk("%s: hw vote count %d\n", __func__, priv->core_hw_vote_count); if (priv->lpass_audio_hw_vote != NULL) { if (--priv->core_audio_vote_count == 0) Loading @@ -1422,6 +1431,8 @@ int bolero_runtime_suspend(struct device *dev) dev_dbg(dev, "%s: Invalid lpass audio hw node\n", __func__); } trace_printk("%s: audio vote count %d\n", __func__, priv->core_audio_vote_count); mutex_unlock(&priv->vote_lock); return 0; Loading
asoc/codecs/bolero/bolero-clk-rsc.c +13 −0 Original line number Diff line number Diff line Loading @@ -129,6 +129,8 @@ int bolero_rsc_clk_reset(struct device *dev, int clk_id) } dev_dbg(priv->dev, "%s: clock reset after ssr, count %d\n", __func__, count); trace_printk("%s: clock reset after ssr, count %d\n", __func__, count); while (count--) { clk_prepare_enable(priv->clk[clk_id]); clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]); Loading Loading @@ -238,6 +240,7 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, char __iomem *clk_muxsel = NULL; int ret = 0; int default_clk_id = priv->default_clk_id[clk_id]; u32 muxsel = 0; clk_muxsel = bolero_clk_rsc_get_clk_muxsel(priv, clk_id); if (!clk_muxsel) { Loading Loading @@ -269,6 +272,9 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, } } iowrite32(0x1, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after enable: %d\n", __func__, muxsel); bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false); } Loading @@ -288,6 +294,9 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, if (!ret) iowrite32(0x0, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after disable: %d\n", __func__, muxsel); if (priv->clk[clk_id + NPL_CLK_OFFSET]) clk_disable_unprepare( priv->clk[clk_id + NPL_CLK_OFFSET]); Loading Loading @@ -504,6 +513,7 @@ int bolero_clk_rsc_request_clock(struct device *dev, if (!priv->dev_up && enable) { dev_err_ratelimited(priv->dev, "%s: SSR is in progress..\n", __func__); trace_printk("%s: SSR is in progress..\n", __func__); ret = -EINVAL; goto err; } Loading Loading @@ -533,6 +543,9 @@ int bolero_clk_rsc_request_clock(struct device *dev, dev_dbg(priv->dev, "%s: clk_cnt: %d for requested clk: %d, enable: %d\n", __func__, priv->clk_cnt[clk_id_req], clk_id_req, enable); trace_printk("%s: clk_cnt: %d for requested clk: %d, enable: %d\n", __func__, priv->clk_cnt[clk_id_req], clk_id_req, enable); mutex_unlock(&priv->rsc_clk_lock); Loading
asoc/codecs/bolero/rx-macro.c +8 −0 Original line number Diff line number Diff line Loading @@ -1284,6 +1284,8 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, } } exit: trace_printk("%s: mclk_enable = %u, dapm = %d clk_users= %d\n", __func__, mclk_enable, dapm, rx_priv->rx_mclk_users); mutex_unlock(&rx_priv->mclk_lock); return ret; } Loading Loading @@ -1369,6 +1371,7 @@ static int rx_macro_event_handler(struct snd_soc_component *component, rx_macro_wcd_clsh_imped_config(component, data, false); break; case BOLERO_MACRO_EVT_SSR_DOWN: trace_printk("%s, enter SSR down\n", __func__); rx_priv->dev_up = false; if (rx_priv->swr_ctrl_data) { swrm_wcd_notify( Loading @@ -1389,6 +1392,7 @@ static int rx_macro_event_handler(struct snd_soc_component *component, } break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); rx_priv->dev_up = true; /* reset swr after ssr/pdr */ rx_priv->reset_swr = true; Loading Loading @@ -3636,6 +3640,8 @@ static int rx_swrm_clock(void *handle, bool enable) mutex_lock(&rx_priv->swr_clk_lock); trace_printk("%s: swrm clock %s\n", __func__, (enable ? "enable" : "disable")); dev_dbg(rx_priv->dev, "%s: swrm clock %s\n", __func__, (enable ? "enable" : "disable")); if (enable) { Loading Loading @@ -3702,6 +3708,8 @@ static int rx_swrm_clock(void *handle, bool enable) } } } trace_printk("%s: swrm clock users %d\n", __func__, rx_priv->swr_clk_users); dev_dbg(rx_priv->dev, "%s: swrm clock users %d\n", __func__, rx_priv->swr_clk_users); exit: Loading
asoc/codecs/bolero/tx-macro.c +42 −15 Original line number Diff line number Diff line Loading @@ -373,6 +373,7 @@ static int tx_macro_event_handler(struct snd_soc_component *component, switch (event) { case BOLERO_MACRO_EVT_SSR_DOWN: trace_printk("%s, enter SSR down\n", __func__); if (tx_priv->swr_ctrl_data) { swrm_wcd_notify( tx_priv->swr_ctrl_data[0].tx_swr_pdev, Loading @@ -392,6 +393,7 @@ static int tx_macro_event_handler(struct snd_soc_component *component, } break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); /* reset swr after ssr/pdr */ tx_priv->reset_swr = true; if (tx_priv->swr_ctrl_data) Loading Loading @@ -883,13 +885,14 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMU: snd_soc_component_update_bits(component, tx_vol_ctl_reg, 0x20, 0x20); if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) { snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00); /* * Minimum 1 clk cycle delay is required as per HW spec */ usleep_range(1000, 1010); } hpf_cut_off_freq = ( snd_soc_component_read32(component, dec_cfg_reg) & TX_HPF_CUT_OFF_FREQ_MASK) >> 5; Loading Loading @@ -917,15 +920,17 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, &tx_priv->tx_hpf_work[decimator].dwork, msecs_to_jiffies(hpf_delay)); snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x03); hpf_gate_reg, 0x03, 0x02); if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x00); /* * Minimum 1 clk cycle delay is required as per HW spec */ usleep_range(1000, 1010); snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00); snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x01); hpf_gate_reg, 0x03, 0x01); /* * 6ms delay is required as per HW spec */ Loading Loading @@ -957,9 +962,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, component, dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK, hpf_cut_off_freq << 5); if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX) snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02); 0x03, 0x02); else snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x03); /* * Minimum 1 clk cycle delay is required * as per HW spec Loading @@ -967,7 +978,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, usleep_range(1000, 1010); snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00); 0x03, 0x01); } } cancel_delayed_work_sync( Loading Loading @@ -2356,6 +2367,9 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, { int ret = 0, clk_tx_ret = 0; trace_printk("%s: clock type %s, enable: %s tx_mclk_users: %d\n", __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"), (enable ? "enable" : "disable"), tx_priv->tx_mclk_users); dev_dbg(tx_priv->dev, "%s: clock type %s, enable: %s tx_mclk_users: %d\n", __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"), Loading @@ -2363,6 +2377,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, if (enable) { if (tx_priv->swr_clk_users == 0) { trace_printk("%s: tx swr clk users 0\n", __func__); ret = msm_cdc_pinctrl_select_active_state( tx_priv->tx_swr_gpio_p); if (ret < 0) { Loading @@ -2378,6 +2393,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, TX_CORE_CLK, true); if (clk_type == TX_MCLK) { trace_printk("%s: requesting TX_MCLK\n", __func__); ret = tx_macro_mclk_enable(tx_priv, 1); if (ret < 0) { if (tx_priv->swr_clk_users == 0) Loading @@ -2390,6 +2406,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, } } if (clk_type == VA_MCLK) { trace_printk("%s: requesting VA_MCLK\n", __func__); ret = bolero_clk_rsc_request_clock(tx_priv->dev, TX_CORE_CLK, VA_CORE_CLK, Loading Loading @@ -2421,6 +2438,8 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, if (tx_priv->swr_clk_users == 0) { dev_dbg(tx_priv->dev, "%s: reset_swr: %d\n", __func__, tx_priv->reset_swr); trace_printk("%s: reset_swr: %d\n", __func__, tx_priv->reset_swr); if (tx_priv->reset_swr) regmap_update_bits(regmap, BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, Loading Loading @@ -2514,6 +2533,7 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, TX_CORE_CLK, false); exit: trace_printk("%s: exit\n", __func__); return ret; } Loading Loading @@ -2590,6 +2610,10 @@ static int tx_macro_swrm_clock(void *handle, bool enable) } mutex_lock(&tx_priv->swr_clk_lock); trace_printk("%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n", __func__, (enable ? "enable" : "disable"), tx_priv->tx_swr_clk_cnt, tx_priv->va_swr_clk_cnt); dev_dbg(tx_priv->dev, "%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n", __func__, (enable ? "enable" : "disable"), Loading Loading @@ -2652,6 +2676,9 @@ static int tx_macro_swrm_clock(void *handle, bool enable) } } trace_printk("%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n", __func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status, tx_priv->va_clk_status); dev_dbg(tx_priv->dev, "%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n", __func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status, Loading