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Commit 612807fe authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Ingo Molnar:
 "Various fixes:

   - 32-bit callgraph bug fix
   - suboptimal event group scheduling bug fix
   - event constraint fixes for Broadwell/Skylake
   - RAPL module name collision fix"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/core: Fix pmu::filter_match for SW-led groups
  x86/perf/intel/rapl: Fix module name collision with powercap intel-rapl
  perf/x86: Fix 32-bit perf user callgraph collection
  perf/x86/intel: Update event constraints when HT is off
parents 977dcf0c 2c81a647

arch/x86/events/core.c

+6 −5
Original line number Diff line number Diff line
@@ -2319,7 +2319,7 @@ void 
perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)

{

	struct stack_frame frame;

	const void __user *fp;

	const unsigned long __user *fp;



	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {

		/* TODO: We don't support guest os callchain now */
@@ -2332,7 +2332,7 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs 
	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))

		return;



	fp = (void __user *)regs->bp;

	fp = (unsigned long __user *)regs->bp;



	perf_callchain_store(entry, regs->ip);
@@ -2345,16 +2345,17 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs 
	pagefault_disable();

	while (entry->nr < entry->max_stack) {

		unsigned long bytes;



		frame.next_frame	     = NULL;

		frame.return_address = 0;



		if (!access_ok(VERIFY_READ, fp, 16))

		if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2))

			break;



		bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8);

		bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));

		if (bytes != 0)

			break;

		bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8);

		bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));

		if (bytes != 0)

			break;

arch/x86/events/intel/Makefile

+2 −2
Original line number Diff line number Diff line 
obj-$(CONFIG_CPU_SUP_INTEL)		+= core.o bts.o cqm.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= ds.o knc.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= lbr.o p4.o p6.o pt.o

obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL)	+= intel-rapl.o

intel-rapl-objs				:= rapl.o

obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL)	+= intel-rapl-perf.o

intel-rapl-perf-objs			:= rapl.o

obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE)	+= intel-uncore.o

intel-uncore-objs			:= uncore.o uncore_nhmex.o uncore_snb.o uncore_snbep.o

obj-$(CONFIG_PERF_EVENTS_INTEL_CSTATE)	+= intel-cstate.o

arch/x86/events/intel/core.c

+29 −0
Original line number Diff line number Diff line
@@ -115,6 +115,10 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly = 
	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */

	INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */



	/*

	 * When HT is off these events can only run on the bottom 4 counters

	 * When HT is on, they are impacted by the HT bug and require EXCL access

	 */

	INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -139,6 +143,10 @@ static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 
	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */

	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */



	/*

	 * When HT is off these events can only run on the bottom 4 counters

	 * When HT is on, they are impacted by the HT bug and require EXCL access

	 */

	INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -182,6 +190,16 @@ struct event_constraint intel_skl_event_constraints[] = { 
	FIXED_EVENT_CONSTRAINT(0x003c, 1),	/* CPU_CLK_UNHALTED.CORE */

	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */

	INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),	/* INST_RETIRED.PREC_DIST */



	/*

	 * when HT is off, these can only run on the bottom 4 counters

	 */

	INTEL_EVENT_CONSTRAINT(0xd0, 0xf),	/* MEM_INST_RETIRED.* */

	INTEL_EVENT_CONSTRAINT(0xd1, 0xf),	/* MEM_LOAD_RETIRED.* */

	INTEL_EVENT_CONSTRAINT(0xd2, 0xf),	/* MEM_LOAD_L3_HIT_RETIRED.* */

	INTEL_EVENT_CONSTRAINT(0xcd, 0xf),	/* MEM_TRANS_RETIRED.* */

	INTEL_EVENT_CONSTRAINT(0xc6, 0xf),	/* FRONTEND_RETIRED.* */



	EVENT_CONSTRAINT_END

};
@@ -250,6 +268,10 @@ static struct event_constraint intel_hsw_event_constraints[] = { 
	/* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */

	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),



	/*

	 * When HT is off these events can only run on the bottom 4 counters

	 * When HT is on, they are impacted by the HT bug and require EXCL access

	 */

	INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -264,6 +286,13 @@ struct event_constraint intel_bdw_event_constraints[] = { 
	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */

	INTEL_UEVENT_CONSTRAINT(0x148, 0x4),	/* L1D_PEND_MISS.PENDING */

	INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),	/* CYCLE_ACTIVITY.CYCLES_L1D_MISS */

	/*

	 * when HT is off, these can only run on the bottom 4 counters

	 */

	INTEL_EVENT_CONSTRAINT(0xd0, 0xf),	/* MEM_INST_RETIRED.* */

	INTEL_EVENT_CONSTRAINT(0xd1, 0xf),	/* MEM_LOAD_RETIRED.* */

	INTEL_EVENT_CONSTRAINT(0xd2, 0xf),	/* MEM_LOAD_L3_HIT_RETIRED.* */

	INTEL_EVENT_CONSTRAINT(0xcd, 0xf),	/* MEM_TRANS_RETIRED.* */

	EVENT_CONSTRAINT_END

};

kernel/events/core.c

+22 −1
Original line number Diff line number Diff line
@@ -1678,12 +1678,33 @@ static bool is_orphaned_event(struct perf_event *event) 
	return event->state == PERF_EVENT_STATE_DEAD;

}



static inline int pmu_filter_match(struct perf_event *event)

static inline int __pmu_filter_match(struct perf_event *event)

{

	struct pmu *pmu = event->pmu;

	return pmu->filter_match ? pmu->filter_match(event) : 1;

}



/*

 * Check whether we should attempt to schedule an event group based on

 * PMU-specific filtering. An event group can consist of HW and SW events,

 * potentially with a SW leader, so we must check all the filters, to

 * determine whether a group is schedulable:

 */

static inline int pmu_filter_match(struct perf_event *event)

{

	struct perf_event *child;



	if (!__pmu_filter_match(event))

		return 0;



	list_for_each_entry(child, &event->sibling_list, group_entry) {

		if (!__pmu_filter_match(child))

			return 0;

	}



	return 1;

}



static inline int

event_filter_match(struct perf_event *event)

{