Commit 612539e8 authored Jan 20, 2012 by Will Deacon Committed by Russell King Jan 23, 2012

ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards



On v7, we use the same cache maintenance instructions for data lines
as for unified lines. This was not the case for v6, where HARVARD_CACHE
was defined to indicate the L1 cache topology.

This patch removes the erroneous compile-time check for HARVARD_CACHE in
proc-v7.S, ensuring that we perform I-side invalidation at boot.

Reported-and-Acked-by: Shawn Guo <shawn.guo@linaro.org>

Cc: stable <stable@vger.kernel.org>
Acked-by: Catalin Marinas <Catalin.Marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 868dbf90

arch/arm/mm/proc-v7.S

+0 −6

Original line number	Diff line number	Diff line
		@@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume)
		* Initialise TLB, Caches, and MMU state ready to switch the MMU
		* on. Return in r0 the new CP15 C1 control register setting.
		*
		* We automatically detect if we have a Harvard cache, and use the
		* Harvard cache control instructions insead of the unified cache
		* control instructions.
		*
		* This should be able to cover all ARMv7 cores.
		*
		* It is assumed that:
		@@ -251,9 +247,7 @@ __v7_setup:
		#endif

		3: mov r10, #0
		#ifdef HARVARD_CACHE
		mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
		#endif
		dsb
		#ifdef CONFIG_MMU
		mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs