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Commit 60eaae2b authored by Tiffany Lin's avatar Tiffany Lin Committed by Mauro Carvalho Chehab
Browse files

[media] arm64: dts: mediatek: Add Video Decoder for MT8173 



Add video decoder node for MT8173

Signed-off-by: default avatarTiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent 86082512

arch/arm64/boot/dts/mediatek/mt8173.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -1051,6 +1051,50 @@ 
			#clock-cells = <1>;

		};



		vcodec_dec: vcodec@16000000 {

			compatible = "mediatek,mt8173-vcodec-dec";

			reg = <0 0x16000000 0 0x100>,	/* VDEC_SYS */

			      <0 0x16020000 0 0x1000>,	/* VDEC_MISC */

			      <0 0x16021000 0 0x800>,	/* VDEC_LD */

			      <0 0x16021800 0 0x800>,	/* VDEC_TOP */

			      <0 0x16022000 0 0x1000>,	/* VDEC_CM */

			      <0 0x16023000 0 0x1000>,	/* VDEC_AD */

			      <0 0x16024000 0 0x1000>,	/* VDEC_AV */

			      <0 0x16025000 0 0x1000>,	/* VDEC_PP */

			      <0 0x16026800 0 0x800>,	/* VDEC_HWD */

			      <0 0x16027000 0 0x800>,	/* VDEC_HWQ */

			      <0 0x16027800 0 0x800>,	/* VDEC_HWB */

			      <0 0x16028400 0 0x400>;	/* VDEC_HWG */

			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;

			mediatek,larb = <&larb1>;

			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,

				 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,

				 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,

				 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,

				 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,

				 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,

				 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,

				 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;

			mediatek,vpu = <&vpu>;

			power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;

			clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,

				 <&topckgen CLK_TOP_UNIVPLL_D2>,

				 <&topckgen CLK_TOP_CCI400_SEL>,

				 <&topckgen CLK_TOP_VDEC_SEL>,

				 <&topckgen CLK_TOP_VCODECPLL>,

				 <&apmixedsys CLK_APMIXED_VENCPLL>,

				 <&topckgen CLK_TOP_VENC_LT_SEL>,

				 <&topckgen CLK_TOP_VCODECPLL_370P5>;

			clock-names = "vcodecpll",

				      "univpll_d2",

				      "clk_cci400_sel",

				      "vdec_sel",

				      "vdecpll",

				      "vencpll",

				      "venc_lt_sel",

				      "vdec_bus_clk_src";

		};



		larb1: larb@16010000 {

			compatible = "mediatek,mt8173-smi-larb";

			reg = <0 0x16010000 0 0x1000>;