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Commit 60cc8a01 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: vidc: Enabling video core power collapse for kona"

parents ec9c1e4a e6c6bbe2

arch/arm64/boot/dts/qcom/kona-vidc.dtsi

+1 −1
Original line number Original line Diff line number Diff line
@@ -10,7 +10,7 @@ 
&soc {

&soc {

	msm_vidc: qcom,vidc@aa00000 {

	msm_vidc: qcom,vidc@aa00000 {

		compatible = "qcom,msm-vidc", "qcom,kona-vidc";

		compatible = "qcom,msm-vidc", "qcom,kona-vidc";

		status = "disabled";

		status = "ok";

		reg = <0x0aa00000 0x00100000>;

		reg = <0x0aa00000 0x00100000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

drivers/media/platform/msm/vidc/msm_vidc_platform.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -161,7 +161,7 @@ static struct msm_vidc_common_data kona_common_data[] = { 
	},

	},

	{

	{

		.key = "qcom,sw-power-collapse",

		.key = "qcom,sw-power-collapse",

		.value = 0,

		.value = 1,

	},

	},

	{

	{

		.key = "qcom,domain-attr-non-fatal-faults",

		.key = "qcom,domain-attr-non-fatal-faults",
@@ -205,7 +205,7 @@ static struct msm_vidc_common_data kona_common_data[] = { 
	},

	},

	{

	{

		.key = "qcom,power-collapse-delay",

		.key = "qcom,power-collapse-delay",

		.value = 15000,

		.value = 1500,

	},

	},

	{

	{

		.key = "qcom,hw-resp-timeout",

		.key = "qcom,hw-resp-timeout",

drivers/media/platform/msm/vidc/venus_hfi.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -1234,6 +1234,10 @@ static inline int __boot_firmware(struct venus_hfi_device *device) 
		dprintk(VIDC_ERR, "Error booting up vidc firmware\n");

		dprintk(VIDC_ERR, "Error booting up vidc firmware\n");

		rc = -ETIME;

		rc = -ETIME;

	}

	}



	/* Enable interrupt before sending commands to venus */

	__write_register(device, VIDC_CPU_CS_H2XSOFTINTEN, 0x1);



	return rc;

	return rc;

}

}

drivers/media/platform/msm/vidc/vidc_hfi_io.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -25,6 +25,7 @@ 
#define VIDC_CPU_CS_VMIMSGAG2		(VIDC_CPU_CS_BASE_OFFS + 0x40)

#define VIDC_CPU_CS_VMIMSGAG2		(VIDC_CPU_CS_BASE_OFFS + 0x40)

#define VIDC_CPU_CS_VMIMSGAG3		(VIDC_CPU_CS_BASE_OFFS + 0x44)

#define VIDC_CPU_CS_VMIMSGAG3		(VIDC_CPU_CS_BASE_OFFS + 0x44)

#define VIDC_CPU_CS_SCIACMD		(VIDC_CPU_CS_BASE_OFFS + 0x48)

#define VIDC_CPU_CS_SCIACMD		(VIDC_CPU_CS_BASE_OFFS + 0x48)

#define VIDC_CPU_CS_H2XSOFTINTEN	(VIDC_CPU_CS_BASE_OFFS + 0x148)





/* HFI_CTRL_STATUS */

/* HFI_CTRL_STATUS */

#define VIDC_CPU_CS_SCIACMDARG0		(VIDC_CPU_CS_BASE_OFFS + 0x4C)

#define VIDC_CPU_CS_SCIACMDARG0		(VIDC_CPU_CS_BASE_OFFS + 0x4C)