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Commit 603b320c authored by Jilai Wang's avatar Jilai Wang
Browse files

msm: npu: Don't enable NPU while SSR is triggered 



Both SSR handling and sending IPCC irq are done in worker thread.
So it's possible that when SSR is triggered but SSR handling
hasn't started, mbox worker will start first and try to enabled NPU.
But it won't succeed because NPU is in bad state. This change is to
prevent mbox worker to enable NPU in this case and also dump the
debug information when SSR is triggered.

Change-Id: I9db40b325d75b067559707c5f044a6a5fb4ed647
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 0e19b93e

drivers/media/platform/msm/npu/npu_dbg.c

+7 −0
Original line number Diff line number Diff line
@@ -103,6 +103,13 @@ static void npu_dump_all_ipc_queue(struct npu_device *npu_dev) 


void npu_dump_debug_info(struct npu_device *npu_dev)

{

	struct npu_host_ctx *host_ctx = &npu_dev->host_ctx;



	if (host_ctx->fw_state != FW_ENABLED) {

		NPU_WARN("NPU is disabled\n");

		return;

	}



	npu_dump_debug_timeout_stats(npu_dev);

	npu_dump_dbg_registers(npu_dev);

	npu_dump_all_ipc_queue(npu_dev);

drivers/media/platform/msm/npu/npu_mgr.c

+7 −0
Original line number Diff line number Diff line
@@ -732,6 +732,7 @@ static int host_error_hdlr(struct npu_device *npu_dev, bool force) 


	if (host_ctx->wdg_irq_sts) {

		NPU_INFO("watchdog irq triggered\n");

		npu_dump_debug_info(npu_dev);

		fw_alive = false;

	}
@@ -899,6 +900,12 @@ static void npu_bridge_mbox_work(struct work_struct *work) 
		return;

	}



	if ((host_ctx->wdg_irq_sts != 0) || (host_ctx->err_irq_sts != 0)) {

		NPU_WARN("SSR is triggered, skip this time\n");

		mutex_unlock(&host_ctx->lock);

		return;

	}



	/* queue or modify delayed work to disable fw */

	mod_delayed_work(host_ctx->wq, &host_ctx->disable_fw_work,

		NPU_MBOX_IDLE_TIMEOUT);