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Commit 603a0c8a authored by Mylène Josserand's avatar Mylène Josserand Committed by Maxime Ripard
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clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig 



The audio DAI needs to set the clock rates of the ac-dig clock.
To make it possible, the parent PLL audio clock rates should
also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.

Signed-off-by: default avatarMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 70421257

drivers/clk/sunxi-ng/ccu-sun8i-a33.c

+1 −1
Original line number Diff line number Diff line
@@ -440,7 +440,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 
			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",

		      0x140, BIT(31), 0);

		      0x140, BIT(31), CLK_SET_RATE_PARENT);

static SUNXI_CCU_GATE(ac_dig_4x_clk,	"ac-dig-4x",	"pll-audio-4x",

		      0x140, BIT(30), 0);

static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",