clk: iproc: add initial common clock support (5fe225c1) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/bcm/Kconfig

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		@@ -7,3 +7,12 @@ config CLK_BCM_KONA
		Enable common clock framework support for Broadcom SoCs
		using "Kona" style clock control units, including those
		in the BCM281xx and BCM21664 families.

		config COMMON_CLK_IPROC
		bool "Broadcom iProc clock support"
		depends on ARCH_BCM_IPROC
		depends on COMMON_CLK
		default ARCH_BCM_IPROC
		help
		Enable common clock framework support for Broadcom SoCs
		based on the iProc architecture

drivers/clk/bcm/Makefile

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		@@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
		obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
		obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
		obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
		obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o

drivers/clk/bcm/clk-iproc-armpll.c

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		/*
		* Copyright (C) 2014 Broadcom Corporation
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License as
		* published by the Free Software Foundation version 2.
		*
		* This program is distributed "as is" WITHOUT ANY WARRANTY of any
		* kind, whether express or implied; without even the implied warranty
		* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/kernel.h>
		#include <linux/slab.h>
		#include <linux/err.h>
		#include <linux/clk-provider.h>
		#include <linux/io.h>
		#include <linux/of.h>
		#include <linux/clkdev.h>
		#include <linux/of_address.h>

		#define IPROC_CLK_MAX_FREQ_POLICY 0x3
		#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
		#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
		#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7

		#define IPROC_CLK_PLLARMA_OFFSET 0xc00
		#define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
		#define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
		#define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
		#define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
		#define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff

		#define IPROC_CLK_PLLARMB_OFFSET 0xc04
		#define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff

		#define IPROC_CLK_PLLARMC_OFFSET 0xc08
		#define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8
		#define IPROC_CLK_PLLARMC_MDIV_MASK 0xff

		#define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
		#define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff

		#define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
		#define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29
		#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
		#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff
		#define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff

		#define IPROC_CLK_ARM_DIV_OFFSET 0xe00
		#define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
		#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf

		#define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
		#define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
		#define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7

		enum iproc_arm_pll_fid {
		ARM_PLL_FID_CRYSTAL_CLK = 0,
		ARM_PLL_FID_SYS_CLK = 2,
		ARM_PLL_FID_CH0_SLOW_CLK = 6,
		ARM_PLL_FID_CH1_FAST_CLK = 7
		};

		struct iproc_arm_pll {
		struct clk_hw hw;
		void __iomem *base;
		unsigned long rate;
		};

		#define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)

		static unsigned int __get_fid(struct iproc_arm_pll *pll)
		{
		u32 val;
		unsigned int policy, fid, active_fid;

		val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
		if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
		policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
		else
		policy = 0;

		/* something is seriously wrong */
		BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);

		val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
		fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
		IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;

		val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
		active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
		(val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
		if (fid != active_fid) {
		pr_debug("%s: fid override %u->%u\n", __func__, fid,
		active_fid);
		fid = active_fid;
		}

		pr_debug("%s: active fid: %u\n", __func__, fid);

		return fid;
		}

		/*
		* Determine the mdiv (post divider) based on the frequency ID being used.
		* There are 4 sources that can be used to derive the output clock rate:
		* - 25 MHz Crystal
		* - System clock
		* - PLL channel 0 (slow clock)
		* - PLL channel 1 (fast clock)
		*/
		static int __get_mdiv(struct iproc_arm_pll *pll)
		{
		unsigned int fid;
		int mdiv;
		u32 val;

		fid = __get_fid(pll);

		switch (fid) {
		case ARM_PLL_FID_CRYSTAL_CLK:
		case ARM_PLL_FID_SYS_CLK:
		mdiv = 1;
		break;

		case ARM_PLL_FID_CH0_SLOW_CLK:
		val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
		mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
		if (mdiv == 0)
		mdiv = 256;
		break;

		case ARM_PLL_FID_CH1_FAST_CLK:
		val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
		mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
		if (mdiv == 0)
		mdiv = 256;
		break;

		default:
		mdiv = -EFAULT;
		}

		return mdiv;
		}

		static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
		{
		u32 val;
		unsigned int ndiv_int, ndiv_frac, ndiv;

		val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
		if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
		/*
		* offset mode is active. Read the ndiv from the PLLARM OFFSET
		* register
		*/
		ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
		IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
		if (ndiv_int == 0)
		ndiv_int = 256;

		ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
		} else {
		/* offset mode not active */
		val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
		ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
		IPROC_CLK_PLLARMA_NDIV_INT_MASK;
		if (ndiv_int == 0)
		ndiv_int = 1024;

		val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
		ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
		}

		ndiv = (ndiv_int << 20) \| ndiv_frac;

		return ndiv;
		}

		/*
		* The output frequency of the ARM PLL is calculated based on the ARM PLL
		* divider values:
		* pdiv = ARM PLL pre-divider
		* ndiv = ARM PLL multiplier
		* mdiv = ARM PLL post divider
		*
		* The frequency is calculated by:
		* ((ndiv * parent clock rate) / pdiv) / mdiv
		*/
		static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
		u32 val;
		int mdiv;
		u64 ndiv;
		unsigned int pdiv;

		/* in bypass mode, use parent rate */
		val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
		if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
		pll->rate = parent_rate;
		return pll->rate;
		}

		/* PLL needs to be locked */
		val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
		if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
		pll->rate = 0;
		return 0;
		}

		pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
		IPROC_CLK_PLLARMA_PDIV_MASK;
		if (pdiv == 0)
		pdiv = 16;

		ndiv = __get_ndiv(pll);
		mdiv = __get_mdiv(pll);
		if (mdiv <= 0) {
		pll->rate = 0;
		return 0;
		}
		pll->rate = (ndiv * parent_rate) >> 20;
		pll->rate = (pll->rate / pdiv) / mdiv;

		pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
		pll->rate, parent_rate);
		pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
		(unsigned int)(ndiv >> 20), pdiv, mdiv);

		return pll->rate;
		}

		static const struct clk_ops iproc_arm_pll_ops = {
		.recalc_rate = iproc_arm_pll_recalc_rate,
		};

		void __init iproc_armpll_setup(struct device_node *node)
		{
		int ret;
		struct clk *clk;
		struct iproc_arm_pll *pll;
		struct clk_init_data init;
		const char *parent_name;

		pll = kzalloc(sizeof(*pll), GFP_KERNEL);
		if (WARN_ON(!pll))
		return;

		pll->base = of_iomap(node, 0);
		if (WARN_ON(!pll->base))
		goto err_free_pll;

		init.name = node->name;
		init.ops = &iproc_arm_pll_ops;
		init.flags = 0;
		parent_name = of_clk_get_parent_name(node, 0);
		init.parent_names = (parent_name ? &parent_name : NULL);
		init.num_parents = (parent_name ? 1 : 0);
		pll->hw.init = &init;

		clk = clk_register(NULL, &pll->hw);
		if (WARN_ON(IS_ERR(clk)))
		goto err_iounmap;

		ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
		if (WARN_ON(ret))
		goto err_clk_unregister;

		return;

		err_clk_unregister:
		clk_unregister(clk);
		err_iounmap:
		iounmap(pll->base);
		err_free_pll:
		kfree(pll);
		}

drivers/clk/bcm/clk-iproc-asiu.c

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		/*
		* Copyright (C) 2014 Broadcom Corporation
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License as
		* published by the Free Software Foundation version 2.
		*
		* This program is distributed "as is" WITHOUT ANY WARRANTY of any
		* kind, whether express or implied; without even the implied warranty
		* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/kernel.h>
		#include <linux/err.h>
		#include <linux/clk-provider.h>
		#include <linux/io.h>
		#include <linux/of.h>
		#include <linux/clkdev.h>
		#include <linux/of_address.h>
		#include <linux/delay.h>

		#include "clk-iproc.h"

		struct iproc_asiu;

		struct iproc_asiu_clk {
		struct clk_hw hw;
		const char *name;
		struct iproc_asiu *asiu;
		unsigned long rate;
		struct iproc_asiu_div div;
		struct iproc_asiu_gate gate;
		};

		struct iproc_asiu {
		void __iomem *div_base;
		void __iomem *gate_base;

		struct clk_onecell_data clk_data;
		struct iproc_asiu_clk *clks;
		};

		#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)

		static int iproc_asiu_clk_enable(struct clk_hw *hw)
		{
		struct iproc_asiu_clk *clk = to_asiu_clk(hw);
		struct iproc_asiu *asiu = clk->asiu;
		u32 val;

		/* some clocks at the ASIU level are always enabled */
		if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
		return 0;

		val = readl(asiu->gate_base + clk->gate.offset);
		val \|= (1 << clk->gate.en_shift);
		writel(val, asiu->gate_base + clk->gate.offset);

		return 0;
		}

		static void iproc_asiu_clk_disable(struct clk_hw *hw)
		{
		struct iproc_asiu_clk *clk = to_asiu_clk(hw);
		struct iproc_asiu *asiu = clk->asiu;
		u32 val;

		/* some clocks at the ASIU level are always enabled */
		if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
		return;

		val = readl(asiu->gate_base + clk->gate.offset);
		val &= ~(1 << clk->gate.en_shift);
		writel(val, asiu->gate_base + clk->gate.offset);
		}

		static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		struct iproc_asiu_clk *clk = to_asiu_clk(hw);
		struct iproc_asiu *asiu = clk->asiu;
		u32 val;
		unsigned int div_h, div_l;

		if (parent_rate == 0) {
		clk->rate = 0;
		return 0;
		}

		/* if clock divisor is not enabled, simply return parent rate */
		val = readl(asiu->div_base + clk->div.offset);
		if ((val & (1 << clk->div.en_shift)) == 0) {
		clk->rate = parent_rate;
		return parent_rate;
		}

		/* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
		div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
		div_h++;
		div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
		div_l++;

		clk->rate = parent_rate / (div_h + div_l);
		pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
		__func__, clk->rate, parent_rate, div_h, div_l);

		return clk->rate;
		}

		static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
		{
		unsigned int div;

		if (rate == 0 \|\| *parent_rate == 0)
		return -EINVAL;

		if (rate == *parent_rate)
		return *parent_rate;

		div = DIV_ROUND_UP(*parent_rate, rate);
		if (div < 2)
		return *parent_rate;

		return *parent_rate / div;
		}

		static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct iproc_asiu_clk *clk = to_asiu_clk(hw);
		struct iproc_asiu *asiu = clk->asiu;
		unsigned int div, div_h, div_l;
		u32 val;

		if (rate == 0 \|\| parent_rate == 0)
		return -EINVAL;

		/* simply disable the divisor if one wants the same rate as parent */
		if (rate == parent_rate) {
		val = readl(asiu->div_base + clk->div.offset);
		val &= ~(1 << clk->div.en_shift);
		writel(val, asiu->div_base + clk->div.offset);
		return 0;
		}

		div = DIV_ROUND_UP(parent_rate, rate);
		if (div < 2)
		return -EINVAL;

		div_h = div_l = div >> 1;
		div_h--;
		div_l--;

		val = readl(asiu->div_base + clk->div.offset);
		val \|= 1 << clk->div.en_shift;
		if (div_h) {
		val &= ~(bit_mask(clk->div.high_width)
		<< clk->div.high_shift);
		val \|= div_h << clk->div.high_shift;
		} else {
		val &= ~(bit_mask(clk->div.high_width)
		<< clk->div.high_shift);
		}
		if (div_l) {
		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
		val \|= div_l << clk->div.low_shift;
		} else {
		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
		}
		writel(val, asiu->div_base + clk->div.offset);

		return 0;
		}

		static const struct clk_ops iproc_asiu_ops = {
		.enable = iproc_asiu_clk_enable,
		.disable = iproc_asiu_clk_disable,
		.recalc_rate = iproc_asiu_clk_recalc_rate,
		.round_rate = iproc_asiu_clk_round_rate,
		.set_rate = iproc_asiu_clk_set_rate,
		};

		void __init iproc_asiu_setup(struct device_node *node,
		const struct iproc_asiu_div *div,
		const struct iproc_asiu_gate *gate,
		unsigned int num_clks)
		{
		int i, ret;
		struct iproc_asiu *asiu;

		if (WARN_ON(!gate \|\| !div))
		return;

		asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
		if (WARN_ON(!asiu))
		return;

		asiu->clk_data.clk_num = num_clks;
		asiu->clk_data.clks = kcalloc(num_clks, sizeof(*asiu->clk_data.clks),
		GFP_KERNEL);
		if (WARN_ON(!asiu->clk_data.clks))
		goto err_clks;

		asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
		if (WARN_ON(!asiu->clks))
		goto err_asiu_clks;

		asiu->div_base = of_iomap(node, 0);
		if (WARN_ON(!asiu->div_base))
		goto err_iomap_div;

		asiu->gate_base = of_iomap(node, 1);
		if (WARN_ON(!asiu->gate_base))
		goto err_iomap_gate;

		for (i = 0; i < num_clks; i++) {
		struct clk_init_data init;
		struct clk *clk;
		const char *parent_name;
		struct iproc_asiu_clk *asiu_clk;
		const char *clk_name;

		clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
		if (WARN_ON(!clk_name))
		goto err_clk_register;

		ret = of_property_read_string_index(node, "clock-output-names",
		i, &clk_name);
		if (WARN_ON(ret))
		goto err_clk_register;

		asiu_clk = &asiu->clks[i];
		asiu_clk->name = clk_name;
		asiu_clk->asiu = asiu;
		asiu_clk->div = div[i];
		asiu_clk->gate = gate[i];
		init.name = clk_name;
		init.ops = &iproc_asiu_ops;
		init.flags = 0;
		parent_name = of_clk_get_parent_name(node, 0);
		init.parent_names = (parent_name ? &parent_name : NULL);
		init.num_parents = (parent_name ? 1 : 0);
		asiu_clk->hw.init = &init;

		clk = clk_register(NULL, &asiu_clk->hw);
		if (WARN_ON(IS_ERR(clk)))
		goto err_clk_register;
		asiu->clk_data.clks[i] = clk;
		}

		ret = of_clk_add_provider(node, of_clk_src_onecell_get,
		&asiu->clk_data);
		if (WARN_ON(ret))
		goto err_clk_register;

		return;

		err_clk_register:
		for (i = 0; i < num_clks; i++)
		kfree(asiu->clks[i].name);
		iounmap(asiu->gate_base);

		err_iomap_gate:
		iounmap(asiu->div_base);

		err_iomap_div:
		kfree(asiu->clks);

		err_asiu_clks:
		kfree(asiu->clk_data.clks);

		err_clks:
		kfree(asiu);
		}

drivers/clk/bcm/clk-iproc-pll.c

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File added.

Preview size limit exceeded, changes collapsed.