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Commit 5fccac6d authored by Niklas Söderlund's avatar Niklas Söderlund Committed by Geert Uytterhoeven
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clk: renesas: r8a7796: Add CSI2 clocks 



Signed-off-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1936be95

drivers/clk/renesas/r8a7796-cpg-mssr.c

+4 −0
Original line number Diff line number Diff line
@@ -103,6 +103,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),



	DEF_DIV6P1("csi0",      R8A7796_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),



	DEF_DIV6_RO("osc",      R8A7796_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),

	DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
@@ -156,6 +158,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("vspd0",		 623,	R8A7796_CLK_S0D2),

	DEF_MOD("vspb",			 626,	R8A7796_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A7796_CLK_S0D1),

	DEF_MOD("csi20",		 714,	R8A7796_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A7796_CLK_CSI0),

	DEF_MOD("du2",			 722,	R8A7796_CLK_S2D1),

	DEF_MOD("du1",			 723,	R8A7796_CLK_S2D1),

	DEF_MOD("du0",			 724,	R8A7796_CLK_S2D1),