Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5fadb510 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'aspeed-4.12-devicetree' of... 

Merge tag 'aspeed-4.12-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into next/dt

Aspeed devicetree updates for 4.12

Updates to the device tree to include upstreamed drivers:

 - SPI flash controller
 - Watchdog
 - ADC

In addition we describe some of the clocks so that upstream kernels can
boot on hardware.

* tag 'aspeed-4.12-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed

:
  arm: dts: aspeed: Describe ADCs for AST2400/AST2500
  ARM: dts: aspeed: romulus: Add UART1
  ARM: dts: aspeed: Update watchdog compatible strings
  ARM: dts: aspeed: Add a fastread property
  ARM: dts: aspeed: Add SPI controller bindings to Romulus
  ARM: dts: aspeed: Make G4 clocks fixed
  ARM: dts: aspeed: Make G5 clocks fixed
  ARM: dts: aspeed: add SPI controller bindings

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 16101f05 78a2569f

arch/arm/boot/dts/aspeed-ast2500-evb.dts

+22 −0
Original line number Diff line number Diff line
@@ -20,6 +20,28 @@ 
	};

};



&fmc {

	status = "okay";

	flash@0 {

		status = "okay";

		m25p,fast-read;

		label = "bmc";

	};

};



&spi1 {

	status = "okay";

	flash@0 {

		status = "okay";

		m25p,fast-read;

		label = "pnor";

	};

};



&spi2 {

	status = "okay";

};



&uart5 {

	status = "okay";

};

arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts

+18 −0
Original line number Diff line number Diff line
@@ -31,6 +31,24 @@ 
	};

};



&fmc {

	status = "okay";

	flash@0 {

		status = "okay";

		m25p,fast-read;

		label = "bmc";

	};

};



&spi {

	status = "okay";

	flash@0 {

		status = "okay";

		m25p,fast-read;

		label = "pnor";

	};

};



&uart5 {

	status = "okay";

};

arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts

+36 −0
Original line number Diff line number Diff line
@@ -31,6 +31,42 @@ 
	};

};



&fmc {

	status = "okay";

	flash@0 {

		status = "okay";

		m25p,fast-read;

		label = "bmc";

	};

};



&spi1 {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_spi1_default>;



	flash@0 {

		status = "okay";

		m25p,fast-read;

		label = "pnor";

	};

};



&uart1 {

	/* Rear RS-232 connector */

	status = "okay";



	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_txd1_default

			&pinctrl_rxd1_default

			&pinctrl_nrts1_default

			&pinctrl_ndtr1_default

			&pinctrl_ndsr1_default

			&pinctrl_ncts1_default

			&pinctrl_ndcd1_default

			&pinctrl_nri1_default>;

};



&uart5 {

	status = "okay";

};

arch/arm/boot/dts/aspeed-g4.dtsi

+78 −31
Original line number Diff line number Diff line
@@ -18,21 +18,41 @@ 
		};

	};



	clocks {

		clk_clkin: clk_clkin {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <48000000>;

		};



	};



	ahb {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		fmc: flash-controller@1e620000 {

			reg = < 0x1e620000 0x94

				0x20000000 0x02000000 >;

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "aspeed,ast2400-fmc";

			status = "disabled";

			interrupts = <19>;

			flash@0 {

				reg = < 0 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

		};



		spi: flash-controller@1e630000 {

			reg = < 0x1e630000 0x18

				0x30000000 0x02000000 >;

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "aspeed,ast2400-spi";

			status = "disabled";

			flash@0 {

				reg = < 0 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

		};



		vic: interrupt-controller@1e6c0080 {

			compatible = "aspeed,ast2400-vic";

			interrupt-controller;
@@ -63,16 +83,48 @@ 
			#size-cells = <1>;

			ranges;



			clk_hpll: clk_hpll@1e6e2070 {

			syscon: syscon@1e6e2000 {

				compatible = "aspeed,g4-scu", "syscon", "simple-mfd";

				reg = <0x1e6e2000 0x1a8>;

				#address-cells = <1>;

				#size-cells = <0>;



                                clk_clkin: clk_clkin {

                                        #clock-cells = <0>;

				compatible = "aspeed,g4-hpll-clock";

				reg = <0x1e6e2070 0x4>;

                                        compatible = "fixed-clock";

                                        clock-frequency = <48000000>;

                                };



                                clk_hpll: clk_hpll@70 {

                                        #clock-cells = <0>;

                                        compatible = "aspeed,g4-hpll-clock", "fixed-clock";

                                        reg = <0x70>;

                                        clocks = <&clk_clkin>;

                                        clock-frequency = <384000000>;

                                };



			syscon: syscon@1e6e2000 {

				compatible = "aspeed,g4-scu", "syscon", "simple-mfd";

				reg = <0x1e6e2000 0x1a8>;

                                clk_ahb: clk_ahb@70 {

                                        #clock-cells = <0>;

                                        compatible = "aspeed,g4-ahb-clock", "fixed-clock";

                                        reg = <0x70>;

                                        clocks = <&clk_hpll>;

                                        clock-frequency = <192000000>;

                                };



                                clk_apb: clk_apb@08 {

                                        #clock-cells = <0>;

                                        compatible = "aspeed,g4-apb-clock", "fixed-clock";

                                        reg = <0x08>;

                                        clocks = <&clk_hpll>;

                                        clock-frequency = <48000000>;

                                };



                                clk_uart: clk_uart@2c{

                                        #clock-cells = <0>;

                                        compatible = "aspeed,g4-uart-clock", "fixed-clock";

                                        reg = <0x2c>;

                                        clock-frequency = <24000000>;

                                };



				pinctrl: pinctrl {

					compatible = "aspeed,g4-pinctrl";
@@ -820,19 +872,6 @@ 
				};

			};



			clk_apb: clk_apb@1e6e2008 {

				#clock-cells = <0>;

				compatible = "aspeed,g4-apb-clock";

				reg = <0x1e6e2008 0x4>;

				clocks = <&clk_hpll>;

			};



			clk_uart: clk_uart@1e6e2008 {

				#clock-cells = <0>;

				compatible = "aspeed,uart-clock";

				reg = <0x1e6e202c 0x4>;

			};



			sram@1e720000 {

				compatible = "mmio-sram";

				reg = <0x1e720000 0x8000>;	// 32K
@@ -859,13 +898,13 @@ 
			};



			wdt1: wdt@1e785000 {

				compatible = "aspeed,wdt";

				compatible = "aspeed,ast2400-wdt";

				reg = <0x1e785000 0x1c>;

				interrupts = <27>;

			};



			wdt2: wdt@1e785020 {

				compatible = "aspeed,wdt";

				compatible = "aspeed,ast2400-wdt";

				reg = <0x1e785020 0x1c>;

				interrupts = <27>;

				clocks = <&clk_apb>;
@@ -932,6 +971,14 @@ 
				no-loopback-test;

				status = "disabled";

			};



			adc: adc@1e6e9000 {

				compatible = "aspeed,ast2400-adc";

				reg = <0x1e6e9000 0xb0>;

				clocks = <&clk_apb>;

				#io-channel-cells = <1>;

				status = "disabled";

			};

		};

	};

};

arch/arm/boot/dts/aspeed-g5.dtsi

+117 −39
Original line number Diff line number Diff line
@@ -24,6 +24,69 @@ 
		#size-cells = <1>;

		ranges;



		fmc: flash-controller@1e620000 {

			reg = < 0x1e620000 0xc4

				0x20000000 0x10000000 >;

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "aspeed,ast2500-fmc";

			status = "disabled";

			interrupts = <19>;

			flash@0 {

				reg = < 0 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

			flash@1 {

				reg = < 1 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

			flash@2 {

				reg = < 2 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

		};



		spi1: flash-controller@1e630000 {

			reg = < 0x1e630000 0xc4

				0x30000000 0x08000000 >;

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "aspeed,ast2500-spi";

			status = "disabled";

			flash@0 {

				reg = < 0 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

			flash@1 {

				reg = < 1 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

		};



		spi2: flash-controller@1e631000 {

			reg = < 0x1e631000 0xc4

				0x38000000 0x08000000 >;

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "aspeed,ast2500-spi";

			status = "disabled";

			flash@0 {

				reg = < 0 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

			flash@1 {

				reg = < 1 >;

				compatible = "jedec,spi-nor";

				status = "disabled";

			};

		};



		vic: interrupt-controller@1e6c0080 {

			compatible = "aspeed,ast2400-vic";

			interrupt-controller;
@@ -54,15 +117,49 @@ 
			#size-cells = <1>;

			ranges;



			clk_clkin: clk_clkin@1e6e2070 {

				#clock-cells = <0>;

				compatible = "aspeed,g5-clkin-clock";

				reg = <0x1e6e2070 0x04>;

			};



			syscon: syscon@1e6e2000 {

				compatible = "aspeed,g5-scu", "syscon", "simple-mfd";

				reg = <0x1e6e2000 0x1a8>;

				#address-cells = <1>;

				#size-cells = <0>;



				clk_clkin: clk_clkin@70 {

					#clock-cells = <0>;

					compatible = "aspeed,g5-clkin-clock", "fixed-clock";

					reg = <0x70>;

					clock-frequency = <24000000>;

				};



				clk_hpll: clk_hpll@24 {

					#clock-cells = <0>;

					compatible = "aspeed,g5-hpll-clock", "fixed-clock";

					reg = <0x24>;

					clocks = <&clk_clkin>;

					clock-frequency = <792000000>;

				};



				clk_ahb: clk_ahb@70 {

					#clock-cells = <0>;

					compatible = "aspeed,g5-ahb-clock", "fixed-clock";

					reg = <0x70>;

					clocks = <&clk_hpll>;

					clock-frequency = <198000000>;

				};



				clk_apb: clk_apb@08 {

					#clock-cells = <0>;

					compatible = "aspeed,g5-apb-clock", "fixed-clock";

					reg = <0x08>;

					clocks = <&clk_hpll>;

					clock-frequency = <24750000>;

				};



				clk_uart: clk_uart@2c {

					#clock-cells = <0>;

					compatible = "aspeed,uart-clock", "fixed-clock";

					reg = <0x2c>;

					clock-frequency = <24000000>;

				};



				pinctrl: pinctrl {

					compatible = "aspeed,g5-pinctrl";
@@ -287,7 +384,6 @@ 
						function = "LAD0";

						groups = "LAD0";

					};



					pinctrl_lad1_default: lad1_default {

						function = "LAD1";

						groups = "LAD1";
@@ -874,33 +970,7 @@ 
					};



				};

			};



			clk_hpll: clk_hpll@1e6e2024 {

				#clock-cells = <0>;

				compatible = "aspeed,g5-hpll-clock";

				reg = <0x1e6e2024 0x4>;

				clocks = <&clk_clkin>;

			};



			clk_ahb: clk_ahb@1e6e2070 {

				#clock-cells = <0>;

				compatible = "aspeed,g5-ahb-clock";

				reg = <0x1e6e2070 0x4>;

				clocks = <&clk_hpll>;

			};



			clk_apb: clk_apb@1e6e2008 {

				#clock-cells = <0>;

				compatible = "aspeed,g5-apb-clock";

				reg = <0x1e6e2008 0x4>;

				clocks = <&clk_hpll>;

			};



			clk_uart: clk_uart@1e6e2008 {

				#clock-cells = <0>;

				compatible = "aspeed,uart-clock";

				reg = <0x1e6e202c 0x4>;

			};



			gfx: display@1e6e6000 {
@@ -936,21 +1006,21 @@ 




			wdt1: wdt@1e785000 {

				compatible = "aspeed,wdt";

				reg = <0x1e785000 0x1c>;

				compatible = "aspeed,ast2500-wdt";

				reg = <0x1e785000 0x20>;

				interrupts = <27>;

			};



			wdt2: wdt@1e785020 {

				compatible = "aspeed,wdt";

				reg = <0x1e785020 0x1c>;

				compatible = "aspeed,ast2500-wdt";

				reg = <0x1e785020 0x20>;

				interrupts = <27>;

				status = "disabled";

			};



			wdt3: wdt@1e785040 {

				compatible = "aspeed,wdt";

				reg = <0x1e785074 0x1c>;

				compatible = "aspeed,ast2500-wdt";

				reg = <0x1e785040 0x20>;

				status = "disabled";

			};
@@ -1044,6 +1114,14 @@ 
				no-loopback-test;

				status = "disabled";

			};



			adc: adc@1e6e9000 {

				compatible = "aspeed,ast2500-adc";

				reg = <0x1e6e9000 0xb0>;

				clocks = <&clk_apb>;

				#io-channel-cells = <1>;

				status = "disabled";

			};

		};

	};

};