Merge "ARM: dts: msm: add smmu devices for lagoon"

	status = "ok";

};

#include "msm-arm-smmu-lagoon.dtsi"

#include "lagoon-pinctrl.dtsi"

#include "lagoon-pm.dtsi"

#include "lagoon-stub-regulator.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {

	kgsl_smmu: arm,smmu-kgsl@3d40000 {

		status = "ok";

		compatible = "qcom,smmu-v2";

		reg = <0x3d40000 0x10000>;

		#iommu-cells = <1>;

		qcom,dynamic;

		qcom,use-3-lvl-tables;

		#global-interrupts = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;

	};

	apps_smmu: apps-smmu@15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x100000>,

			<0x15182000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;

		anoc_1_tbu: anoc_1_tbu@15185000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15185000 0x1000>,

				<0x15182200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

		};

		anoc_2_tbu: anoc_2_tbu@15189000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15189000 0x1000>,

				<0x15182208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

		};

		mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1518d000 0x1000>,

				<0x15182210 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x800 0x400>;

		};

		mnoc_sf_0_tbu: mnoc_sf_0_tbu@15191000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15191000 0x1000>,

				<0x15182218 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0xc00 0x400>;

		};

		adsp_tbu: adsp_tbu@15195000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15195000 0x1000>,

				<0x15182220 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1000 0x400>;

		};

		compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15199000 0x1000>,

				<0x15182228 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1400 0x400>;

		};

		pcie_tbu: pcie_tbu@1519d000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1519d000 0x1000>,

				<0x15182230 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1800 0x400>;

		};

	};

};