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Commit 5ee60aa4 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Greg Kroah-Hartman
Browse files

arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E 



[ Upstream commit dcabb06bf127b3e0d3fbc94a2b65dd56c2725851 ]

UniPhier LD20 and PXs3 boards have RTL8211E ethernet phy, and the phy have
the RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY
pins.

After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), the delays are working correctly, however, "rgmii" means
no delay and the phy doesn't work. So need to set the phy-mode to
"rgmii-id" to show that RX/TX delays are enabled.

Fixes: c73730ee ("arm64: dts: uniphier: add AVE ethernet node")
Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 55c2b0dd

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -610,7 +610,7 @@ 
			clocks = <&sys_clk 6>;

			reset-names = "ether";

			resets = <&sys_rst 6>;

			phy-mode = "rgmii";

			phy-mode = "rgmii-id";

			local-mac-address = [00 00 00 00 00 00];

			socionext,syscon-phy-mode = <&soc_glue 0>;

arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -416,7 +416,7 @@ 
			clocks = <&sys_clk 6>;

			reset-names = "ether";

			resets = <&sys_rst 6>;

			phy-mode = "rgmii";

			phy-mode = "rgmii-id";

			local-mac-address = [00 00 00 00 00 00];

			socionext,syscon-phy-mode = <&soc_glue 0>;
@@ -437,7 +437,7 @@ 
			clocks = <&sys_clk 7>;

			reset-names = "ether";

			resets = <&sys_rst 7>;

			phy-mode = "rgmii";

			phy-mode = "rgmii-id";

			local-mac-address = [00 00 00 00 00 00];

			socionext,syscon-phy-mode = <&soc_glue 1>;