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Commit 5e683389 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Only allow Cavium OCTEON to be configured for boards that support it 



Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
CC: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 64e71303

arch/mips/Kconfig

+6 −2
Original line number Diff line number Diff line
@@ -603,7 +603,7 @@ config CAVIUM_OCTEON_SIMULATOR 
	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select CPU_CAVIUM_OCTEON

	select SYS_HAS_CPU_CAVIUM_OCTEON

	help

	  The Octeon simulator is software performance model of the Cavium

	  Octeon Processor. It supports simulating Octeon processors on x86
@@ -618,7 +618,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_HAS_EARLY_PRINTK

	select CPU_CAVIUM_OCTEON

	select SYS_HAS_CPU_CAVIUM_OCTEON

	select SWAP_IO_SPACE

	help

	  This option supports all of the Octeon reference boards from Cavium
@@ -1234,6 +1234,7 @@ config CPU_SB1 


config CPU_CAVIUM_OCTEON

	bool "Cavium Octeon processor"

	depends on SYS_HAS_CPU_CAVIUM_OCTEON

	select IRQ_CPU

	select IRQ_CPU_OCTEON

	select CPU_HAS_PREFETCH
@@ -1314,6 +1315,9 @@ config SYS_HAS_CPU_RM9000 
config SYS_HAS_CPU_SB1

	bool



config SYS_HAS_CPU_CAVIUM_OCTEON

	bool



#

# CPU may reorder R->R, R->W, W->R, W->W

# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC