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Commit 5dd20bba authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher
Browse files

drm/radeon: Set MASTER_UPDATE_MODE to 0 again 



With the previous change, it's safe to let page flips take effect
anytime during a vertical blank period.

This can avoid delaying a flip by a frame in some cases where we get to
radeon_flip_work_func -> adev->mode_info.funcs->page_flip during a
vertical blank period.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b8fc75cf

drivers/gpu/drm/radeon/atombios_crtc.c

+4 −4
Original line number Diff line number Diff line
@@ -1433,8 +1433,8 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

	       (viewport_w << 16) | viewport_h);



	/* set pageflip to happen only at start of vblank interval (front porch) */

	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);

	/* set pageflip to happen anywhere in vblank interval */

	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);



	if (!atomic && fb && fb != crtc->primary->fb) {

		radeon_fb = to_radeon_framebuffer(fb);
@@ -1632,8 +1632,8 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 
	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

	       (viewport_w << 16) | viewport_h);



	/* set pageflip to happen only at start of vblank interval (front porch) */

	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);

	/* set pageflip to happen anywhere in vblank interval */

	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);



	if (!atomic && fb && fb != crtc->primary->fb) {

		radeon_fb = to_radeon_framebuffer(fb);

drivers/gpu/drm/radeon/evergreen.c

+1 −2
Original line number Diff line number Diff line
@@ -2878,9 +2878,8 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s 
	for (i = 0; i < rdev->num_crtc; i++) {

		if (save->crtc_enabled[i]) {

			tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);

			if ((tmp & 0x7) != 3) {

			if ((tmp & 0x7) != 0) {

				tmp &= ~0x7;

				tmp |= 0x3;

				WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

+1 −2
Original line number Diff line number Diff line
@@ -406,9 +406,8 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 
	for (i = 0; i < rdev->num_crtc; i++) {

		if (save->crtc_enabled[i]) {

			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);

			if ((tmp & 0x7) != 3) {

			if ((tmp & 0x7) != 0) {

				tmp &= ~0x7;

				tmp |= 0x3;

				WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);