Loading asoc/codecs/wcd937x/wcd937x.c +16 −0 Original line number Diff line number Diff line Loading @@ -1020,6 +1020,22 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00); usleep_range(10000, 10010); /* disable EAR CnP FSM */ snd_soc_component_update_bits(component, WCD937X_EAR_EAR_EN_REG, 0x02, 0x00); /* toggle EAR PA to let PA control registers take effect */ snd_soc_component_update_bits(component, WCD937X_ANA_EAR, 0x80, 0x80); snd_soc_component_update_bits(component, WCD937X_ANA_EAR, 0x80, 0x00); /* enable EAR CnP FSM */ snd_soc_component_update_bits(component, WCD937X_EAR_EAR_EN_REG, 0x02, 0x02); break; }; return ret; Loading asoc/msm-pcm-routing-v2.h +2 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef _MSM_PCM_ROUTING_H #define _MSM_PCM_ROUTING_H Loading Loading @@ -212,6 +212,7 @@ #define LPASS_BE_WSA_CDC_DMA_RX_0 "WSA_CDC_DMA_RX_0" #define LPASS_BE_WSA_CDC_DMA_TX_0 "WSA_CDC_DMA_TX_0" #define LPASS_BE_WSA_CDC_DMA_TX_0_VI "WSA_CDC_DMA_TX_0_VI" #define LPASS_BE_WSA_CDC_DMA_RX_1 "WSA_CDC_DMA_RX_1" #define LPASS_BE_WSA_CDC_DMA_TX_1 "WSA_CDC_DMA_TX_1" #define LPASS_BE_WSA_CDC_DMA_TX_2 "WSA_CDC_DMA_TX_2" Loading soc/swr-mstr-ctrl.c +14 −11 Original line number Diff line number Diff line Loading @@ -2171,20 +2171,21 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: break; case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: if (swrm->state == SWR_MSTR_UP) if (swrm->state == SWR_MSTR_UP) { dev_dbg(swrm->dev, "%s:SWR Master is already up\n", __func__); else } else { dev_err_ratelimited(swrm->dev, "%s: SWR wokeup during clock stop\n", __func__); /* It might be possible the slave device gets reset * and slave interrupt gets missed. So re-enable * Host IRQ and process slave pending /* It might be possible the slave device gets * reset and slave interrupt gets missed. So * re-enable Host IRQ and process slave pending * interrupts, if any. */ swrm_enable_slave_irq(swrm); } break; default: dev_err_ratelimited(swrm->dev, Loading Loading @@ -2489,9 +2490,6 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x02; reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x03; reg[len] = SWRM_INTERRUPT_CLEAR; value[len++] = 0xFFFFFFFF; Loading @@ -2503,6 +2501,9 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWR_MSTR_RX_SWRM_CPU_INTERRUPT_EN; value[len++] = swrm->intr_mask; reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x03; swr_master_bulk_write(swrm, reg, value, len); if (!swrm_check_link_status(swrm, 0x1)) { Loading Loading @@ -2675,6 +2676,8 @@ static int swrm_probe(struct platform_device *pdev) SWRM_NUM_AUTO_ENUM_SLAVES); ret = -EINVAL; goto err_pdata_fail; } else { swrm->master.num_dev = swrm->num_dev; } } Loading Loading
asoc/codecs/wcd937x/wcd937x.c +16 −0 Original line number Diff line number Diff line Loading @@ -1020,6 +1020,22 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00); usleep_range(10000, 10010); /* disable EAR CnP FSM */ snd_soc_component_update_bits(component, WCD937X_EAR_EAR_EN_REG, 0x02, 0x00); /* toggle EAR PA to let PA control registers take effect */ snd_soc_component_update_bits(component, WCD937X_ANA_EAR, 0x80, 0x80); snd_soc_component_update_bits(component, WCD937X_ANA_EAR, 0x80, 0x00); /* enable EAR CnP FSM */ snd_soc_component_update_bits(component, WCD937X_EAR_EAR_EN_REG, 0x02, 0x02); break; }; return ret; Loading
asoc/msm-pcm-routing-v2.h +2 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef _MSM_PCM_ROUTING_H #define _MSM_PCM_ROUTING_H Loading Loading @@ -212,6 +212,7 @@ #define LPASS_BE_WSA_CDC_DMA_RX_0 "WSA_CDC_DMA_RX_0" #define LPASS_BE_WSA_CDC_DMA_TX_0 "WSA_CDC_DMA_TX_0" #define LPASS_BE_WSA_CDC_DMA_TX_0_VI "WSA_CDC_DMA_TX_0_VI" #define LPASS_BE_WSA_CDC_DMA_RX_1 "WSA_CDC_DMA_RX_1" #define LPASS_BE_WSA_CDC_DMA_TX_1 "WSA_CDC_DMA_TX_1" #define LPASS_BE_WSA_CDC_DMA_TX_2 "WSA_CDC_DMA_TX_2" Loading
soc/swr-mstr-ctrl.c +14 −11 Original line number Diff line number Diff line Loading @@ -2171,20 +2171,21 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: break; case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: if (swrm->state == SWR_MSTR_UP) if (swrm->state == SWR_MSTR_UP) { dev_dbg(swrm->dev, "%s:SWR Master is already up\n", __func__); else } else { dev_err_ratelimited(swrm->dev, "%s: SWR wokeup during clock stop\n", __func__); /* It might be possible the slave device gets reset * and slave interrupt gets missed. So re-enable * Host IRQ and process slave pending /* It might be possible the slave device gets * reset and slave interrupt gets missed. So * re-enable Host IRQ and process slave pending * interrupts, if any. */ swrm_enable_slave_irq(swrm); } break; default: dev_err_ratelimited(swrm->dev, Loading Loading @@ -2489,9 +2490,6 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x02; reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x03; reg[len] = SWRM_INTERRUPT_CLEAR; value[len++] = 0xFFFFFFFF; Loading @@ -2503,6 +2501,9 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWR_MSTR_RX_SWRM_CPU_INTERRUPT_EN; value[len++] = swrm->intr_mask; reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x03; swr_master_bulk_write(swrm, reg, value, len); if (!swrm_check_link_status(swrm, 0x1)) { Loading Loading @@ -2675,6 +2676,8 @@ static int swrm_probe(struct platform_device *pdev) SWRM_NUM_AUTO_ENUM_SLAVES); ret = -EINVAL; goto err_pdata_fail; } else { swrm->master.num_dev = swrm->num_dev; } } Loading