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Commit 5d99cc59 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc 



The conventions is to put SoC devices under 'soc' node. In fact other
our DTSes (like exynos3250.dtsi or exynos5410.dtsi) already follow it.
Adjust exynos5250 and exynos5420 DTSI to follow this convention. This is
also necessary for the upcoming change in exynos5410.dtsi to inherit
from common exynos5.dtsi.

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
parent e3daf8e5

arch/arm/boot/dts/exynos5.dtsi

+144 −137
Original line number Diff line number Diff line
@@ -30,6 +30,12 @@ 
		serial3 = &serial_3;

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		chipid@10000000 {

			compatible = "samsung,exynos4210-chipid";

			reg = <0x10000000 0x100>;
@@ -170,3 +176,4 @@ 
			status = "disabled";

		};

	};

};

arch/arm/boot/dts/exynos5250.dtsi

+800 −797
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ 
		};

	};



	soc: soc {

		sysram@02020000 {

			compatible = "mmio-sram";

			reg = <0x02020000 0x30000>;
@@ -153,9 +154,10 @@ 
				     <1 14 0xf08>,

				     <1 11 0xf08>,

				     <1 10 0xf08>;

		/* Unfortunately we need this since some versions of U-Boot

		 * on Exynos don't set the CNTFRQ register, so we need the

		 * value from DT.

			/*

			 * Unfortunately we need this since some versions

			 * of U-Boot on Exynos don't set the CNTFRQ register,

			 * so we need the value from DT.

			 */

			clock-frequency = <24000000>;

		};
@@ -278,25 +280,6 @@ 
			#include "exynos4412-tmu-sensor-conf.dtsi"

		};



	thermal-zones {

		cpu_thermal: cpu-thermal {

			polling-delay-passive = <0>;

			polling-delay = <0>;

			thermal-sensors = <&tmu 0>;



			cooling-maps {

				map0 {

				     /* Corresponds to 800MHz at freq_table */

				     cooling-device = <&cpu0 9 9>;

				};

				map1 {

				     /* Corresponds to 200MHz at freq_table */

				     cooling-device = <&cpu0 15 15>;

			       };

		       };

		};

	};



		sata: sata@122F0000 {

			compatible = "snps,dwc-ahci";

			samsung,sata-freq = <66>;
@@ -982,6 +965,26 @@ 
		};

	};



	thermal-zones {

		cpu_thermal: cpu-thermal {

			polling-delay-passive = <0>;

			polling-delay = <0>;

			thermal-sensors = <&tmu 0>;



			cooling-maps {

				map0 {

				     /* Corresponds to 800MHz at freq_table */

				     cooling-device = <&cpu0 9 9>;

				};

				map1 {

				     /* Corresponds to 200MHz at freq_table */

				     cooling-device = <&cpu0 15 15>;

			       };

		       };

		};

	};

};



&dp {

	power-domains = <&pd_disp1>;

	clocks = <&clock CLK_DP>;

arch/arm/boot/dts/exynos5420.dtsi

+1383 −1380
Original line number Diff line number Diff line
@@ -46,6 +46,12 @@ 
		usbdrdphy1 = &usbdrd_phy1;

	};



	/*

	 * The 'cpus' node is not present here but instead it is provided

	 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.

	 */



	soc: soc {

		cluster_a15_opp_table: opp_table0 {

			compatible = "operating-points-v2";

			opp-shared;
@@ -156,11 +162,6 @@ 
			};

		};



	/*

	 * The 'cpus' node is not present here but instead it is provided

	 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.

	 */



		cci: cci@10d20000 {

			compatible = "arm,cci-400";

			#address-cells = <1>;
@@ -466,9 +467,10 @@ 
				#dma-requests = <1>;

				/*

				 * MDMA1 can support both secure and non-secure

			 * AXI transactions. When this is enabled in the kernel

			 * for boards that run in secure mode, we are getting

			 * imprecise external aborts causing the kernel to oops.

				 * AXI transactions. When this is enabled in

				 * the kernel for boards that run in secure

				 * mode, we are getting imprecise external

				 * aborts causing the kernel to oops.

				 */

				status = "disabled";

			};
@@ -836,29 +838,6 @@ 
			#include "exynos4412-tmu-sensor-conf.dtsi"

		};



	thermal-zones {

		cpu0_thermal: cpu0-thermal {

			thermal-sensors = <&tmu_cpu0>;

			#include "exynos5420-trip-points.dtsi"

		};

		cpu1_thermal: cpu1-thermal {

		       thermal-sensors = <&tmu_cpu1>;

		       #include "exynos5420-trip-points.dtsi"

		};

		cpu2_thermal: cpu2-thermal {

		       thermal-sensors = <&tmu_cpu2>;

		       #include "exynos5420-trip-points.dtsi"

		};

		cpu3_thermal: cpu3-thermal {

		       thermal-sensors = <&tmu_cpu3>;

		       #include "exynos5420-trip-points.dtsi"

		};

		gpu_thermal: gpu-thermal {

		       thermal-sensors = <&tmu_gpu>;

		       #include "exynos5420-trip-points.dtsi"

		};

	};



		watchdog: watchdog@101D0000 {

			compatible = "samsung,exynos5420-wdt";

			reg = <0x101D0000 0x100>;
@@ -1524,6 +1503,30 @@ 
		};

	};



	thermal-zones {

		cpu0_thermal: cpu0-thermal {

			thermal-sensors = <&tmu_cpu0>;

			#include "exynos5420-trip-points.dtsi"

		};

		cpu1_thermal: cpu1-thermal {

		       thermal-sensors = <&tmu_cpu1>;

		       #include "exynos5420-trip-points.dtsi"

		};

		cpu2_thermal: cpu2-thermal {

		       thermal-sensors = <&tmu_cpu2>;

		       #include "exynos5420-trip-points.dtsi"

		};

		cpu3_thermal: cpu3-thermal {

		       thermal-sensors = <&tmu_cpu3>;

		       #include "exynos5420-trip-points.dtsi"

		};

		gpu_thermal: gpu-thermal {

		       thermal-sensors = <&tmu_gpu>;

		       #include "exynos5420-trip-points.dtsi"

		};

	};

};



&dp {

	clocks = <&clock CLK_DP1>;

	clock-names = "dp";