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Commit 5d708680 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915/bdw: Implement Wa4x4STCOptimizationDisable:bdw 



Not implementing this W/A can lead to hangs.

Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Rafael Barbalho <rafael.barbalho@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e568af1c

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Diff line number Diff line
@@ -974,6 +974,7 @@ enum punit_power_well { 
#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)

#define CACHE_MODE_1		0x7004 /* IVB+ */

#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)

#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)



#define GEN6_BLITTER_ECOSKPD	0x221d0

#define   GEN6_BLITTER_LOCK_SHIFT			16

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -4882,6 +4882,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
	/* WaDisableSDEUnitClockGating:bdw */

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/* Wa4x4STCOptimizationDisable:bdw */

	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));

}



static void haswell_init_clock_gating(struct drm_device *dev)