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Commit 5d60e057 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.16-rc4' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Pretty much run of the mill drm fixes.

  amdgpu:
   - power management fixes
   - some display fixes
   - one ppc 32-bit dma fix

  i915:
   - two display fixes
   - three gem fixes

  sun4i:
   - display regression fixes

  nouveau:
   - display regression fix

  virtio-gpu:
   - dumb airlied ioctl fix"

* tag 'drm-fixes-for-v4.16-rc4' of git://people.freedesktop.org/~airlied/linux: (25 commits)
  drm/amdgpu: skip ECC for SRIOV in gmc late_init
  drm/amd/amdgpu: Correct VRAM width for APUs with GMC9
  drm/amdgpu: fix&cleanups for wb_clear
  drm/amdgpu: Correct sdma_v4 get_wptr(v2)
  drm/amd/powerplay: fix power over limit on Fiji
  drm/amdgpu:Fixed wrong emit frame size for enc
  drm/amdgpu: move WB_FREE to correct place
  drm/amdgpu: only flush hotplug work without DC
  drm/amd/display: check for ipp before calling cursor operations
  drm/i915: Make global seqno known in i915_gem_request_execute tracepoint
  drm/i915: Clear the in-use marker on execbuf failure
  drm/i915/cnl: Fix PORT_TX_DW5/7 register address
  drm/i915/audio: fix check for av_enc_map overflow
  drm/i915: Fix rsvd2 mask when out-fence is returned
  virtio-gpu: fix ioctl and expose the fixed status to userspace.
  drm/sun4i: Protect the TCON pixel clocks
  drm/sun4i: Enable the output on the pins (tcon0)
  drm/nouveau: prefer XBGR2101010 for addfb ioctl
  drm/radeon: insist on 32-bit DMA for Cedar on PPC64/PPC64LE
  drm/amd/display: VGA black screen from s3 when attached to hook
  ...
parents 2120447b 93dfdf9f

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -1156,7 +1156,7 @@ static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 
/*

/*

 * Writeback

 * Writeback

 */

 */

#define AMDGPU_MAX_WB 512	/* Reserve at most 512 WB slots for amdgpu-owned rings. */

#define AMDGPU_MAX_WB 128	/* Reserve at most 128 WB slots for amdgpu-owned rings. */





struct amdgpu_wb {

struct amdgpu_wb {

	struct amdgpu_bo	*wb_obj;

	struct amdgpu_bo	*wb_obj;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+10 −16
Original line number Original line Diff line number Diff line
@@ -492,7 +492,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev) 
		memset(&adev->wb.used, 0, sizeof(adev->wb.used));

		memset(&adev->wb.used, 0, sizeof(adev->wb.used));





		/* clear wb memory */

		/* clear wb memory */

		memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));

		memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);

	}

	}





	return 0;

	return 0;
@@ -530,8 +530,9 @@ int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) 
 */

 */

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)

{

{

	wb >>= 3;

	if (wb < adev->wb.num_wb)

	if (wb < adev->wb.num_wb)

		__clear_bit(wb >> 3, adev->wb.used);

		__clear_bit(wb, adev->wb.used);

}

}





/**

/**
@@ -1455,11 +1456,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) 
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.hw)

		if (!adev->ip_blocks[i].status.hw)

			continue;

			continue;

		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {

			amdgpu_free_static_csa(adev);

			amdgpu_device_wb_fini(adev);

			amdgpu_device_vram_scratch_fini(adev);

		}





		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&

		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&

			adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {

			adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
@@ -1486,6 +1482,13 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) 
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.sw)

		if (!adev->ip_blocks[i].status.sw)

			continue;

			continue;



		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {

			amdgpu_free_static_csa(adev);

			amdgpu_device_wb_fini(adev);

			amdgpu_device_vram_scratch_fini(adev);

		}



		r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);

		r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);

		/* XXX handle errors */

		/* XXX handle errors */

		if (r) {

		if (r) {
@@ -2284,14 +2287,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) 
				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);

				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);

			}

			}

			drm_modeset_unlock_all(dev);

			drm_modeset_unlock_all(dev);

		} else {

			/*

			 * There is no equivalent atomic helper to turn on

			 * display, so we defined our own function for this,

			 * once suspend resume is supported by the atomic

			 * framework this will be reworked

			 */

			amdgpu_dm_display_resume(adev);

		}

		}

	}

	}
@@ -2726,7 +2721,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
	if (amdgpu_device_has_dc_support(adev)) {

	if (amdgpu_device_has_dc_support(adev)) {

		if (drm_atomic_helper_resume(adev->ddev, state))

		if (drm_atomic_helper_resume(adev->ddev, state))

			dev_info(adev->dev, "drm resume failed:%d\n", r);

			dev_info(adev->dev, "drm resume failed:%d\n", r);

		amdgpu_dm_display_resume(adev);

	} else {

	} else {

		drm_helper_resume_force_mode(adev->ddev);

		drm_helper_resume_force_mode(adev->ddev);

	}

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -75,7 +75,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man, 
static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)

static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)

{

{

	struct amdgpu_gtt_mgr *mgr = man->priv;

	struct amdgpu_gtt_mgr *mgr = man->priv;



	spin_lock(&mgr->lock);

	drm_mm_takedown(&mgr->mm);

	drm_mm_takedown(&mgr->mm);

	spin_unlock(&mgr->lock);

	spin_unlock(&mgr->lock);

	kfree(mgr);

	kfree(mgr);

drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -257,6 +257,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) 
	r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);

	r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);

	if (r) {

	if (r) {

		adev->irq.installed = false;

		adev->irq.installed = false;

		if (!amdgpu_device_has_dc_support(adev))

			flush_work(&adev->hotplug_work);

			flush_work(&adev->hotplug_work);

		cancel_work_sync(&adev->reset_work);

		cancel_work_sync(&adev->reset_work);

		return r;

		return r;
@@ -282,6 +283,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev) 
		adev->irq.installed = false;

		adev->irq.installed = false;

		if (adev->irq.msi_enabled)

		if (adev->irq.msi_enabled)

			pci_disable_msi(adev->pdev);

			pci_disable_msi(adev->pdev);

		if (!amdgpu_device_has_dc_support(adev))

			flush_work(&adev->hotplug_work);

			flush_work(&adev->hotplug_work);

		cancel_work_sync(&adev->reset_work);

		cancel_work_sync(&adev->reset_work);

	}

	}

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -634,7 +634,7 @@ static int gmc_v9_0_late_init(void *handle) 
	for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)

	for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)

		BUG_ON(vm_inv_eng[i] > 16);

		BUG_ON(vm_inv_eng[i] > 16);





	if (adev->asic_type == CHIP_VEGA10) {

	if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {

		r = gmc_v9_0_ecc_available(adev);

		r = gmc_v9_0_ecc_available(adev);

		if (r == 1) {

		if (r == 1) {

			DRM_INFO("ECC is active.\n");

			DRM_INFO("ECC is active.\n");
@@ -682,6 +682,9 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 
	adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);

	adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);

	if (!adev->mc.vram_width) {

	if (!adev->mc.vram_width) {

		/* hbm memory channel size */

		/* hbm memory channel size */

		if (adev->flags & AMD_IS_APU)

			chansize = 64;

		else

			chansize = 128;

			chansize = 128;





		tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);

		tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);