Merge "msm: cvp: Extend CVP NOC wait for idle timeout" (5c265f58) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/media/platform/msm/cvp/cvp_core_hfi.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -240,6 +240,7 @@ struct iris_hfi_device {
	unsigned long scaled_rate;		unsigned long scaled_rate;
	struct msm_cvp_gov_data bus_vote;		struct msm_cvp_gov_data bus_vote;
	bool power_enabled;		bool power_enabled;
			bool reg_dumped;
	struct mutex lock;		struct mutex lock;
	msm_cvp_callback callback;		msm_cvp_callback callback;
	struct cvp_mem_addr iface_q_table;		struct cvp_mem_addr iface_q_table;

drivers/media/platform/msm/cvp/cvp_hfi.c

+31 −19

Original line number	Original line	Diff line number	Diff line
	@@ -1387,7 +1387,7 @@ static void cvp_dump_csr(struct iris_hfi_device *dev)

	if (!dev)		if (!dev)
	return;		return;
	if (!dev->power_enabled)		if (!dev->power_enabled \|\| dev->reg_dumped)
	return;		return;
	reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);		reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
	dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);		dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
	@@ -1395,16 +1395,19 @@ static void cvp_dump_csr(struct iris_hfi_device *dev)
	dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);		dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
	reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);		reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
	dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);		dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
			reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
			dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
	reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);		reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
	dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);		dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
	reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);		reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
	dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);		dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
	reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);		reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
	dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);		dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
	reg = __read_register(dev, CVP_CC_MVS0C_GDSCR);
	dprintk(CVP_ERR, "CVP_CC_MVS0C_GDSCR: %x\n", reg);
	reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);		reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
	dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);		dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
			reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
			dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
			dev->reg_dumped = true;
	}		}

	static int iris_hfi_flush_debug_queue(void *dev)		static int iris_hfi_flush_debug_queue(void *dev)
	@@ -2231,6 +2234,7 @@ static int iris_hfi_core_init(void *device)
	}		}

	__set_state(dev, IRIS_STATE_INIT);		__set_state(dev, IRIS_STATE_INIT);
			dev->reg_dumped = false;

	dprintk(CVP_DBG, "Dev_Virt: %pa, Reg_Virt: %pK\n",		dprintk(CVP_DBG, "Dev_Virt: %pa, Reg_Virt: %pK\n",
	&dev->cvp_hal_data->firmware_base,		&dev->cvp_hal_data->firmware_base,
	@@ -2315,7 +2319,7 @@ static int iris_hfi_core_release(void *dev)
	}		}

	mutex_lock(&device->lock);		mutex_lock(&device->lock);
	dprintk(CVP_DBG, "Core releasing\n");		dprintk(CVP_WARN, "Core releasing\n");
	if (device->res->pm_qos_latency_us &&		if (device->res->pm_qos_latency_us &&
	pm_qos_request_active(&device->qos))		pm_qos_request_active(&device->qos))
	pm_qos_remove_request(&device->qos);		pm_qos_remove_request(&device->qos);
	@@ -4429,7 +4433,9 @@ static inline int __suspend(struct iris_hfi_device *device)

	static void power_off_iris2(struct iris_hfi_device *device)		static void power_off_iris2(struct iris_hfi_device *device)
	{		{
	u32 lpi_status, reg_status = 0, count = 0, max_count = 10;		u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
			u32 pc_ready, wfi_status, sbm_ln0_low;
			u32 main_sbm_ln0_low, main_sbm_ln1_high;

	if (!device->power_enabled)		if (!device->power_enabled)
	return;		return;
	@@ -4448,18 +4454,26 @@ static void power_off_iris2(struct iris_hfi_device *device)
	__read_register(device,		__read_register(device,
	CVP_AON_WRAPPER_MVP_NOC_LPI_STATUS);		CVP_AON_WRAPPER_MVP_NOC_LPI_STATUS);
	reg_status = lpi_status & BIT(0);		reg_status = lpi_status & BIT(0);
	dprintk(CVP_DBG,
	"Noc: lpi_status %x noc_status %x (count %d)\n",
	lpi_status, reg_status, count);

	/* Wait for noc lpi status to be set */		/* Wait for noc lpi status to be set */
	usleep_range(50, 100);		usleep_range(50, 100);
	count++;		count++;
	}		}
			dprintk(CVP_DBG,
			"Noc: lpi_status %x noc_status %x (count %d)\n",
			lpi_status, reg_status, count);
	if (count == max_count) {		if (count == max_count) {
			wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
			pc_ready = __read_register(device, CVP_CTRL_STATUS);
			sbm_ln0_low =
			__read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
			main_sbm_ln0_low = __read_register(device,
			CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW);
			main_sbm_ln1_high = __read_register(device,
			CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH);
	dprintk(CVP_WARN,		dprintk(CVP_WARN,
	"NOC not in qaccept status %x %x\n",		"NOC not in qaccept status %x %x %x %x %x %x %x\n",
	reg_status, lpi_status);		reg_status, lpi_status, wfi_status, pc_ready,
			sbm_ln0_low, main_sbm_ln0_low, main_sbm_ln1_high);
	}		}

	/* HPG 6.1.2 Step 3, debug bridge to low power */		/* HPG 6.1.2 Step 3, debug bridge to low power */
	@@ -4471,14 +4485,13 @@ static void power_off_iris2(struct iris_hfi_device *device)
	lpi_status = __read_register(device,		lpi_status = __read_register(device,
	CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);		CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
	reg_status = lpi_status & 0x7;		reg_status = lpi_status & 0x7;
	dprintk(CVP_DBG,
	"DBLP Set : lpi_status %d reg_status %d (count %d)\n",
	lpi_status, reg_status, count);

	/* Wait for debug bridge lpi status to be set */		/* Wait for debug bridge lpi status to be set */
	usleep_range(50, 100);		usleep_range(50, 100);
	count++;		count++;
	}		}
			dprintk(CVP_DBG,
			"DBLP Set : lpi_status %d reg_status %d (count %d)\n",
			lpi_status, reg_status, count);
	if (count == max_count) {		if (count == max_count) {
	dprintk(CVP_WARN,		dprintk(CVP_WARN,
	"DBLP Set: status %x %x\n", reg_status, lpi_status);		"DBLP Set: status %x %x\n", reg_status, lpi_status);
	@@ -4492,12 +4505,12 @@ static void power_off_iris2(struct iris_hfi_device *device)
	while (lpi_status && count < max_count) {		while (lpi_status && count < max_count) {
	lpi_status = __read_register(device,		lpi_status = __read_register(device,
	CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);		CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
	dprintk(CVP_DBG,
	"DBLP Release: lpi_status %d(count %d)\n",
	lpi_status, count);
	usleep_range(50, 100);		usleep_range(50, 100);
	count++;		count++;
	}		}
			dprintk(CVP_DBG,
			"DBLP Release: lpi_status %d(count %d)\n",
			lpi_status, count);
	if (count == max_count) {		if (count == max_count) {
	dprintk(CVP_WARN,		dprintk(CVP_WARN,
	"DBLP Release: lpi_status %x\n", lpi_status);		"DBLP Release: lpi_status %x\n", lpi_status);
	@@ -4665,7 +4678,6 @@ static void __unload_fw(struct iris_hfi_device *device)
	if (device->state != IRIS_STATE_DEINIT)		if (device->state != IRIS_STATE_DEINIT)
	flush_workqueue(device->iris_pm_workq);		flush_workqueue(device->iris_pm_workq);

	__vote_buses(device, NULL, 0);
	subsystem_put(device->resources.fw.cookie);		subsystem_put(device->resources.fw.cookie);
	__interface_queues_release(device);		__interface_queues_release(device);
	call_iris_op(device, power_off, device);		call_iris_op(device, power_off, device);

drivers/media/platform/msm/cvp/cvp_hfi_io.h

+8 −1

Original line number	Original line	Diff line number	Diff line
	@@ -105,11 +105,12 @@
	#define CVP_WRAPPER_INTR_CLEAR_A2H_BMSK 0x4		#define CVP_WRAPPER_INTR_CLEAR_A2H_BMSK 0x4
	#define CVP_WRAPPER_INTR_CLEAR_A2H_SHFT 0x2		#define CVP_WRAPPER_INTR_CLEAR_A2H_SHFT 0x2
	#define CVP_WRAPPER_CPU_STATUS (CVP_WRAPPER_TZ_BASE_OFFS + 0x10)		#define CVP_WRAPPER_CPU_STATUS (CVP_WRAPPER_TZ_BASE_OFFS + 0x10)
	#define CVP_WRAPPER_CPU_CLOCK_CONFIG (CVP_WRAPPER_TZ_BASE_OFFS + 0x50)
	#define CVP_WRAPPER_CPU_CGC_DIS (CVP_WRAPPER_BASE_OFFS + 0x2010)		#define CVP_WRAPPER_CPU_CGC_DIS (CVP_WRAPPER_BASE_OFFS + 0x2010)

			#define CVP_WRAPPER_CPU_CLOCK_CONFIG (CVP_WRAPPER_BASE_OFFS + 0x50)
	#define CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (CVP_WRAPPER_BASE_OFFS + 0x54)		#define CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (CVP_WRAPPER_BASE_OFFS + 0x54)
	#define CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS (CVP_WRAPPER_BASE_OFFS + 0x58)		#define CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS (CVP_WRAPPER_BASE_OFFS + 0x58)
			#define CVP_WRAPPER_CORE_CLOCK_CONFIG (CVP_WRAPPER_BASE_OFFS + 0x88)

	#define CVP_CTRL_INIT CVP_CPU_CS_SCIACMD		#define CVP_CTRL_INIT CVP_CPU_CS_SCIACMD

	@@ -177,8 +178,13 @@
	#define CVP_NOC_ERR_ERRLOG2_HIGH_OFFS (CVP_NOC_BASE_OFFS + 0xB4)		#define CVP_NOC_ERR_ERRLOG2_HIGH_OFFS (CVP_NOC_BASE_OFFS + 0xB4)
	#define CVP_NOC_ERR_ERRLOG3_LOW_OFFS (CVP_NOC_BASE_OFFS + 0xB8)		#define CVP_NOC_ERR_ERRLOG3_LOW_OFFS (CVP_NOC_BASE_OFFS + 0xB8)
	#define CVP_NOC_ERR_ERRLOG3_HIGH_OFFS (CVP_NOC_BASE_OFFS + 0xBC)		#define CVP_NOC_ERR_ERRLOG3_HIGH_OFFS (CVP_NOC_BASE_OFFS + 0xBC)
			#define CVP_NOC_SBM_SENSELN0_LOW (CVP_NOC_BASE_OFFS + 0x300)

	#define CVP_NOC_CORE_BASE_OFFS 0x00010000		#define CVP_NOC_CORE_BASE_OFFS 0x00010000
			#define CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW \
			(CVP_NOC_CORE_BASE_OFFS + 0x1100)
			#define CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH \
			(CVP_NOC_CORE_BASE_OFFS + 0x110C)
	#define CVP_NOC_CORE_ERR_SWID_LOW_OFFS \		#define CVP_NOC_CORE_ERR_SWID_LOW_OFFS \
	(CVP_NOC_CORE_BASE_OFFS + 0x1200)		(CVP_NOC_CORE_BASE_OFFS + 0x1200)
	#define CVP_NOC_CORE_ERR_SWID_HIGH_OFFS \		#define CVP_NOC_CORE_ERR_SWID_HIGH_OFFS \
	@@ -213,4 +219,5 @@
	#define CVP_CC_BASE_OFFS 0x000F0000		#define CVP_CC_BASE_OFFS 0x000F0000
	#define CVP_CC_MVS0C_GDSCR (CVP_CC_BASE_OFFS + 0xBF8)		#define CVP_CC_MVS0C_GDSCR (CVP_CC_BASE_OFFS + 0xBF8)
	#define CVP_CC_MVS1C_GDSCR (CVP_CC_BASE_OFFS + 0xC98)		#define CVP_CC_MVS1C_GDSCR (CVP_CC_BASE_OFFS + 0xC98)
			#define CVP_CC_MVS1C_CBCR (CVP_CC_BASE_OFFS + 0xCD4)
	#endif		#endif

drivers/media/platform/msm/cvp/msm_cvp.c

+5 −4

Original line number	Original line	Diff line number	Diff line
	@@ -1624,7 +1624,7 @@ static int adjust_bw_freqs(void)
	struct clock_info *cl;		struct clock_info *cl;
	struct allowed_clock_rates_table *tbl = NULL;		struct allowed_clock_rates_table *tbl = NULL;
	unsigned int tbl_size;		unsigned int tbl_size;
	unsigned int cvp_min_rate, cvp_max_rate, max_bw;		unsigned int cvp_min_rate, cvp_max_rate, max_bw, min_bw;
	struct cvp_power_level rt_pwr = {0}, nrt_pwr = {0};		struct cvp_power_level rt_pwr = {0}, nrt_pwr = {0};
	unsigned long tmp, core_sum, op_core_sum, bw_sum;		unsigned long tmp, core_sum, op_core_sum, bw_sum;
	int i, rc = 0;		int i, rc = 0;
	@@ -1640,6 +1640,7 @@ static int adjust_bw_freqs(void)
	cvp_max_rate = tbl[tbl_size - 1].clock_rate;		cvp_max_rate = tbl[tbl_size - 1].clock_rate;
	bus = &core->resources.bus_set.bus_tbl[1];		bus = &core->resources.bus_set.bus_tbl[1];
	max_bw = bus->range[1];		max_bw = bus->range[1];
			min_bw = max_bw/10;

	aggregate_power_request(core, &nrt_pwr, &rt_pwr, cvp_max_rate);		aggregate_power_request(core, &nrt_pwr, &rt_pwr, cvp_max_rate);
	dprintk(CVP_DBG, "PwrReq nrt %u %u rt %u %u\n",		dprintk(CVP_DBG, "PwrReq nrt %u %u rt %u %u\n",
	@@ -1675,10 +1676,10 @@ static int adjust_bw_freqs(void)
	}		}

	bw_sum = rt_pwr.bw_sum + nrt_pwr.bw_sum;		bw_sum = rt_pwr.bw_sum + nrt_pwr.bw_sum;
	if (bw_sum > max_bw)		bw_sum = (bw_sum > max_bw) ? max_bw : bw_sum;
	bw_sum = max_bw;		bw_sum = (bw_sum < min_bw) ? min_bw : bw_sum;

	dprintk(CVP_DBG, "%s %lld %lld\n", __func__,		dprintk(CVP_PROF, "%s %lld %lld\n", __func__,
	core_sum, bw_sum);		core_sum, bw_sum);
	if (!cl->has_scaling) {		if (!cl->has_scaling) {
	dprintk(CVP_ERR, "Cannot scale CVP clock\n");		dprintk(CVP_ERR, "Cannot scale CVP clock\n");