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Commit 5c20872c authored by Bao D. Nguyen's avatar Bao D. Nguyen
Browse files

ARM: dts: msm: enable UFS HS-G4 related attributes for Kona 



UFS 3.0 devices support HS-G4 bus speed modes and these devices
need additional voltage supply to be enabled. In addition, this
change adds new bus bandwidth votes for HS-G4.

Change-Id: Ie4c19e89be2daf8f6739bacdf04f7faa1770ef06
Signed-off-by: default avatarBao D. Nguyen <nguyenb@codeaurora.org>
parent 88711c66

arch/arm64/boot/dts/qcom/kona-cdp.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -42,7 +42,9 @@ 
	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8150_l17>;

	vcc-voltage-level = <2950000 2960000>;

	vccq-supply = <&pm8150_l6>;

	vccq2-supply = <&pm8150_s4>;

	vccq-max-microamp = <800000>;

	vcc-max-microamp = <800000>;

	vccq2-max-microamp = <800000>;

arch/arm64/boot/dts/qcom/kona-mtp.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -42,8 +42,10 @@ 
	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8150_l17>;

	vcc-voltage-level = <2950000 2960000>;

	vccq-supply = <&pm8150_l6>;

	vccq2-supply = <&pm8150_s4>;

	vcc-max-microamp = <800000>;

	vccq-max-microamp = <800000>;

	vccq2-max-microamp = <800000>;



	qcom,vddp-ref-clk-supply = <&pm8150_l6>;

arch/arm64/boot/dts/qcom/kona-qrd.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -81,8 +81,10 @@ 
	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8150_l17>;

	vcc-voltage-level = <2950000 2960000>;

	vccq-supply = <&pm8150_l6>;

	vccq2-supply = <&pm8150_s4>;

	vcc-max-microamp = <800000>;

	vccq-max-microamp = <800000>;

	vccq2-max-microamp = <800000>;



	qcom,vddp-ref-clk-supply = <&pm8150_l6>;

arch/arm64/boot/dts/qcom/kona.dtsi

+10 −5
Original line number Diff line number Diff line
@@ -1778,7 +1778,7 @@ 
			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";

		qcom,msm-bus,num-cases = <22>;

		qcom,msm-bus,num-cases = <26>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		/*
@@ -1803,12 +1803,15 @@ 
		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */

		<123 512 4194304 0>, <1 757 204800 0>,  /* HS G4 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */

		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */

		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */

		<123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */

		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */

		<123 512 4194304 0>, <1 757 204800 0>,  /* HS G4 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */

		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated
@@ -1818,15 +1821,17 @@ 
		 * bindwidth (IB) needs to be given a proper value too.

		 */

		<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */

		<123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */

		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",



		"MAX";



		/* PM QoS */