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Commit 5c1c176f authored by Rishabh Bhatnagar's avatar Rishabh Bhatnagar
Browse files

ARM: dts: msm: Correct mem timer register address kona. 



Correct the register addresses for memory-mapped arm timer.

Change-Id: I1f3aae6ca1d23af360134bcfb72b46aec52c5525
Signed-off-by: default avatarRishabh Bhatnagar <rishabhb@codeaurora.org>
parent 40f58568

arch/arm64/boot/dts/qcom/kona.dtsi

+24 −24
Original line number Diff line number Diff line
@@ -217,61 +217,61 @@ 
		clock-frequency = <19200000>;

	};



	timer@0x17c00000{

	timer@0x17c20000{

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		compatible = "arm,armv7-timer-mem";

		reg = <0x17c00000 0x1000>;

		reg = <0x17c20000 0x1000>;

		clock-frequency = <19200000>;



		frame@0x17c10000 {

		frame@0x17c21000 {

			frame-number = <0>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c10000 0x1000>,

			      <0x17c20000 0x1000>;

			reg = <0x17c21000 0x1000>,

			      <0x17c22000 0x1000>;

		};



		frame@17c30000 {

		frame@17c23000 {

			frame-number = <1>;

			interrupts = <GIC_SPI 8 0x4>;

			reg = <0x17c30000 0x1000>;

			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c23000 0x1000>;

			status = "disabled";

		};



		frame@17c40000 {

		frame@17c25000 {

			frame-number = <2>;

			interrupts = <GIC_SPI 9 0x4>;

			reg = <0x17c40000 0x1000>;

			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c25000 0x1000>;

			status = "disabled";

		};



		frame@17c60000 {

		frame@17c27000 {

			frame-number = <3>;

			interrupts = <GIC_SPI 10 0x4>;

			reg = <0x17c60000 0x1000>;

			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c27000 0x1000>;

			status = "disabled";

		};



		frame@17c70000 {

		frame@17c29000 {

			frame-number = <4>;

			interrupts = <GIC_SPI 11 0x4>;

			reg = <0x17c70000 0x1000>;

			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c29000 0x1000>;

			status = "disabled";

		};



		frame@17c800000 {

		frame@17c2b0000 {

			frame-number = <5>;

			interrupts = <GIC_SPI 12 0x4>;

			reg = <0x17c80000 0x1000>;

			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c2b000 0x1000>;

			status = "disabled";

		};



		frame@17c90000 {

		frame@17c2d000 {

			frame-number = <6>;

			interrupts = <GIC_SPI 13 0x4>;

			reg = <0x17c90000 0x1000>;

			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c2d000 0x1000>;

			status = "disabled";

		};

	};