Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5c1a9693 authored by Abhishek Sahu's avatar Abhishek Sahu Committed by Stephen Boyd
Browse files

clk: qcom: ipq4019: Add the nodes for pcnoc 



The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
This PCNOC clock is critical and should not be turned off so
setting CRITICAL flag also.

Signed-off-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent d83dcace

drivers/clk/qcom/gcc-ipq4019.c

+39 −0
Original line number Diff line number Diff line
@@ -1520,6 +1520,43 @@ static struct clk_fepll gcc_fepllwcss5g_clk = { 
	.pll_vco = &gcc_fepll_vco,

};



static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = {

	F(48000000,  P_XO,	 1, 0, 0),

	F(100000000, P_FEPLL200, 2, 0, 0),

	{ }

};



static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = {

	.cmd_rcgr = 0x21024,

	.hid_width = 5,

	.parent_map = gcc_xo_200_500_map,

	.freq_tbl = ftbl_gcc_pcnoc_ahb_clk,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_pcnoc_ahb_clk_src",

		.parent_names = gcc_xo_200_500,

		.num_parents = 3,

		.ops = &clk_rcg2_ops,

	},

};



static struct clk_branch pcnoc_clk_src = {

	.halt_reg = 0x21030,

	.clkr = {

		.enable_reg = 0x21030,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "pcnoc_clk_src",

			.parent_names = (const char *[]){

				"gcc_pcnoc_ahb_clk_src",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

			.flags = CLK_SET_RATE_PARENT |

				CLK_IS_CRITICAL,

		},

	},

};



static struct clk_regmap *gcc_ipq4019_clocks[] = {

	[AUDIO_CLK_SRC] = &audio_clk_src.clkr,

	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -1588,6 +1625,8 @@ static struct clk_regmap *gcc_ipq4019_clocks[] = { 
	[GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr,

	[GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr,

	[GCC_APSS_CPU_PLLDIV_CLK] = &gcc_apss_cpu_plldiv_clk.cdiv.clkr,

	[GCC_PCNOC_AHB_CLK_SRC] = &gcc_pcnoc_ahb_clk_src.clkr,

	[GCC_PCNOC_AHB_CLK] = &pcnoc_clk_src.clkr,

};



static const struct qcom_reset_map gcc_ipq4019_resets[] = {

include/dt-bindings/clock/qcom,gcc-ipq4019.h

+1 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ 
#define GCC_FEPLL_WCSS2G_CLK				72

#define GCC_FEPLL_WCSS5G_CLK				73

#define GCC_APSS_CPU_PLLDIV_CLK				74

#define GCC_PCNOC_AHB_CLK_SRC				75



#define WIFI0_CPU_INIT_RESET				0

#define WIFI0_RADIO_SRIF_RESET				1