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Commit 5be13340 authored by David S. Miller's avatar David S. Miller
Browse files
parents f2c31e32 a5d5a914
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+1 −5
Original line number Diff line number Diff line
@@ -309,11 +309,7 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
	u8 i;
	u32 val;

	if (ah->is_pciexpress != true)
		return;

	/* Do not touch SerDes registers */
	if (ah->config.pcie_powersave_enable == 2)
	if (ah->is_pciexpress != true || ah->aspm_enabled != true)
		return;

	/* Nothing to do on restore for 11N */
+1 −5
Original line number Diff line number Diff line
@@ -519,11 +519,7 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
					 int restore,
					 int power_off)
{
	if (ah->is_pciexpress != true)
		return;

	/* Do not touch SerDes registers */
	if (ah->config.pcie_powersave_enable == 2)
	if (ah->is_pciexpress != true || ah->aspm_enabled != true)
		return;

	/* Nothing to do on restore for 11N */
+9 −2
Original line number Diff line number Diff line
@@ -318,6 +318,14 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
}

static void ath9k_hw_aspm_init(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);

	if (common->bus_ops->aspm_init)
		common->bus_ops->aspm_init(common);
}

/* This should work for all families including legacy */
static bool ath9k_hw_chip_test(struct ath_hw *ah)
{
@@ -378,7 +386,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_powersave_enable = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
@@ -598,7 +605,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)


	if (ah->is_pciexpress)
		ath9k_hw_configpcipowersave(ah, 0, 0);
		ath9k_hw_aspm_init(ah);
	else
		ath9k_hw_disablepcie(ah);

+2 −1
Original line number Diff line number Diff line
@@ -219,7 +219,6 @@ struct ath9k_ops_config {
	int additional_swba_backoff;
	int ack_6mb;
	u32 cwm_ignore_extcca;
	u8 pcie_powersave_enable;
	bool pcieSerDesWrite;
	u8 pcie_clock_req;
	u32 pcie_waen;
@@ -673,6 +672,7 @@ struct ath_hw {

	bool sw_mgmt_crypto;
	bool is_pciexpress;
	bool aspm_enabled;
	bool is_monitoring;
	bool need_an_top2_fixup;
	u16 tx_trig_level;
@@ -874,6 +874,7 @@ struct ath_bus_ops {
	bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
	void (*bt_coex_prep)(struct ath_common *common);
	void (*extn_synch_en)(struct ath_common *common);
	void (*aspm_init)(struct ath_common *common);
};

static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
+2 −0
Original line number Diff line number Diff line
@@ -670,8 +670,10 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
static void ath9k_init_txpower_limits(struct ath_softc *sc)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath9k_channel *curchan = ah->curchan;

	ah->txchainmask = common->tx_chainmask;
	if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
		ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
	if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
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